公开(公告)号：US06557138B1

公开(公告)日：2003-04-29

申请号：US09500707

申请日：2000-02-09

Applicant: Alberto Modelli

Inventor： Alberto Modelli

IPC: H03M1300

CPC classification number: G06F11/1072 ,  G11C11/5621 ,  G11C29/00

Abstract: A method for correction of errors in a word stored in multi-bit memory cells includes associating a full error code, which includes bit error codes and a set error code, for each set of bits of the word stored in a single memory cell. The method includes associating, with each single error, a bit error code which is not associated with other errors and which is indicative of a position of the bit in the word. The set error code is computed based on the bit error codes associated with the bits in the set. The method also checks to make sure that the full error code for the set has not already been associated with other errors. If the error code has already been used for another error, then the method changes both the set error code and at least one of the bit error codes.

Abstract translation: 用于校正存储在多位存储器单元中的字中的错误的方法包括将存储在单个存储器单元中的单词的每组的相关联的全错误代码（包括位错码和设定的错误代码）相关联。 该方法包括将每个单个错误与不与其他错误相关联的位错误代码相关联，并且该位错误代码指示该位中该位的位置。 基于与集合中的位相关联的位错误代码来计算设置的错误代码。 该方法还检查以确保集合的完整错误代码尚未与其他错误相关联。 如果错误代码已被用于另一个错误，则该方法将更改设置的错误代码和至少一个位错误代码。

公开(公告)号：US06734490B2

公开(公告)日：2004-05-11

申请号：US09919341

申请日：2001-07-30

Applicant: David Esseni ,  Luca Selmi ,  Roberto Bez ,  Alberto Modelli

Inventor： David Esseni ,  Luca Selmi ,  Roberto Bez ,  Alberto Modelli

IPC: H01L29788

CPC classification number: H01L29/66825 ,  G11C16/0416 ,  H01L27/11521 ,  H01L29/7885

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

Abstract translation: 存储单元形成在形成沟道区域的P型半导体材料的主体中，并且在沟道区域的两个相对侧容纳N型漏极和源极区域。 浮动栅极区域在沟道区域的上方延伸。 P型电荷注入区域至少部分地在沟道区域和漏极区域之间在体内连续地延伸到漏极区域。 N型基极区域在漏极区域，电荷注入区域和沟道区域之间延伸。 电荷注入区域和漏极区域被特殊的接触区域偏置，以使由电荷注入区域和基极区域形成的PN结正向偏置。 这样在电荷注入区域中产生的孔直接通过基底区域注入到体内，在那里它们通过冲击产生被注入到浮动栅极区域的电子。

公开(公告)号：US5990526A

公开(公告)日：1999-11-23

申请号：US27343

申请日：1998-02-20

Applicant: Roberto Bez ,  Alberto Modelli

Inventor： Roberto Bez ,  Alberto Modelli

IPC: H01L21/8247 ,  H01L29/76 ,  H01L27/10 ,  H01L29/792 ,  H01L29/94

CPC classification number: H01L27/11519 ,  H01L27/11521

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type, a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in the first well, an array of memory cells formed within the second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in the second well, and a control gate electrode. The memory array comprises a first plurality of strips of conductive material extending over the second well in a first direction and forming rows of memory cells, a second plurality of strips of conductive material extending over the second well in a second direction substantially orthogonal to the first direction and forming columns of memory cells, each strip of the second plurality electrically contacting the first electrodes of a respective group of memory cells, a third plurality of strips of conductive material extending over the second well in the second direction and intercalated to the strips of the second plurality, electrically contacting the second electrodes of the cells. A fourth plurality of strips of conductive material is provided extending over the second well in the second direction and intercalated to the strips of the second and the third pluralities, electrically contacting the second well in a succession of contact points distributed longitudinally to each strip of the fourth plurality.

Abstract translation: 一种存储器件，包括具有第一类型的掺杂剂的半导体材料衬底，在衬底中形成的具有第二类型的掺杂剂的第一半导体材料; 具有形成在第一阱中的第一类型的掺杂剂的第二半导体材料，形成在第二阱内的存储器单元的阵列。 每个存储单元包括分别由形成在第二阱中的第二类型的掺杂剂的第一和第二掺杂区域以及控制栅极电极分别形成的第一电极和第二电极。 所述存储器阵列包括在第一方向上在所述第二阱上延伸的第一多个导电材料条，并且形成行的存储器单元;第二多个导电材料条，沿第二方向在第二方向上延伸，所述第二方向基本上垂直于所述第一 方向和形成存储器单元的列，第二多个的每个条带电接触相应组的存储单元的第一电极;第三多个导电材料条，沿着第二方向在第二阱上延伸并插入到 所述第二多个电极与所述电池的第二电极电接触。 提供了第四多个导电材料条，其沿着第二方向在第二阱上延伸并且插入第二和第三多个的条带中，并且将第二阱的一系列接触点电连接到纵向分配到每个条带 第四个。

公开(公告)号：US6071778A

公开(公告)日：2000-06-06

申请号：US389955

申请日：1999-09-03

Applicant: Roberto Bez ,  Alberto Modelli

Inventor： Roberto Bez ,  Alberto Modelli

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type; a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in said first well; an array of memory cells formed within said second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in said second well, and a control gate electrode. The memory array comprises a first plurality of strips of conductive material extending over said second well in a first direction and forming rows of memory cells, a second plurality of strips of conductive material extending over said second well in a second direction substantially orthogonal to said first direction and forming columns of memory cells, each strip of said second plurality electrically contacting the first electrodes of a respective group of memory cells, a third plurality of strips of conductive material extending over said second well in said second direction and intercalated to the strips of the second plurality, electrically contacting the second electrodes of the cells. A fourth plurality of strips of conductive material is provided extending over said second well in said second direction and intercalated to the strips of said second and third pluralities, electrically contacting the second well in a succession of contact points distributed longitudinally to each strip of said fourth plurality.

Abstract translation: 一种存储器件，包括具有第一类型的掺杂剂的半导体材料衬底; 在衬底中形成有第二类型的掺杂剂的第一半导体材料; 具有形成在所述第一阱中的第一类型的掺杂剂的第二半导体材料; 形成在所述第二井内的一组存储单元。 每个存储单元包括分别由形成在所述第二阱中的第二类型掺杂剂的第一掺杂区域和第二掺杂区域形成的第一电极和第二电极以及控制栅电极。 所述存储器阵列包括在第一方向上在所述第二阱上延伸的第一多个导电材料条，并且形成行存储器单元;第二多个导电材料条，沿着与所述第一 方向和形成存储器单元的列，所述第二多个的每个条带电接触相应组的存储单元的第一电极;第三多个导电材料条，沿着所述第二方向在所述第二阱上延伸并插入到 所述第二多个电极与所述电池的第二电极电接触。 提供了第四多个导电材料条带，其在所述第二方向上在所述第二阱上延伸并且插入所述第二和第三多个的条带中，并且将所述第二阱的一系列接触点电连接到所述第四部分 复数。

公开(公告)号：US06366496B1

公开(公告)日：2002-04-02

申请号：US09631187

申请日：2000-08-02

Applicant: Guido Torelli ,  Alberto Modelli ,  Alessandro Manstretta

Inventor： Guido Torelli ,  Alberto Modelli ,  Alessandro Manstretta

IPC: G11C1134

CPC classification number: G11C11/5621 ,  G11C11/5628

Abstract: When programming, for each programming pulse, a threshold voltage whose value is increased with respect to the previous programming pulse is applied to the gate terminal of each cell to be programmed. After an initial step, the increase of threshold voltage of the cell being programmed becomes equal to the applied gate voltage increase. In order to reduce the global programming time, keeping a small variability interval of threshold voltages associated with each level, to pass from a threshold level to a following one, each cell to be programmed is supplied with a plurality of consecutive pulses without verify, until it is immediately below the voltage level to be programmed, and then a verify step is performed, followed by subsequent programming and verify steps until the cell to be programmed reaches the desired threshold value.

Abstract translation: 当编程时，对于每个编程脉冲，其值相对于先前编程脉冲增加的阈值电压被施加到要被编程的每个单元的栅极端子。 在初始步骤之后，被编程的单元的阈值电压的增加等于施加的栅极电压增加。 为了减少全局编程时间，保持与每个电平相关联的阈值电压的小变化间隔从阈值电平传递到随后的一个，要编程的每个单元被提供多个连续脉冲而不进行验证，直到 它立即低于要编程的电压电平，然后执行验证步骤，然后进行后续编程和验证步骤，直到要编程的单元格达到所需的阈值。

公开(公告)号：US6128219A

公开(公告)日：2000-10-03

申请号：US428683

申请日：1999-10-27

Applicant: Federico Pio ,  Enrico Gomiero ,  Alberto Modelli ,  Paola Paruzzi

Inventor： Federico Pio ,  Enrico Gomiero ,  Alberto Modelli ,  Paola Paruzzi

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/06

CPC classification number: G11C16/0433 ,  G11C16/34

Abstract: A test structure is formed by an array of memory cells connected in parallel and including each a memory transistor and a select transistor connected in series. The gate terminals of the select transistors of all memory cells are biased to a value next to the threshold voltage of the select transistors. Therefore, in each memory cell, the drain current is limited by the memory transistor for control gate voltages below the threshold voltage of the memory transistor, and by the select transistor at higher voltages; for high control gate voltages, the drain current is clamped to a constant maximum value. Since the clamping effect of the select transistors acts on each memory cell, the total maximum current of the test structure may be held below a value causing a limitation in the current generated by the entire array because of the resistance in series to the output of the test structure. Thus also the right side of the threshold distribution may be evaluated and the presence of defective cells causing injection of electrons in the floating gate of the memory transistors may be detected.

Abstract translation: 测试结构由并行连接的存储单元的阵列形成，并且包括串联连接的存储晶体管和选择晶体管。 所有存储单元的选择晶体管的栅极端子被偏置成与选择晶体管的阈值电压相邻的值。 因此，在每个存储单元中，漏极电流被存储晶体管限制，用于控制栅极电压低于存储晶体管的阈值电压，并由选择晶体管处于较高电压; 对于高控制栅极电压，漏极电流被钳位到恒定的最大值。 由于选择晶体管的钳位效应作用于每个存储单元，所以测试结构的总最大电流可以被保持在导致由整个阵列产生的电流限制的值，因为与 测试结构。 因此，可以评估阈值分布的右侧，并且可以检测到在存储晶体管的浮动栅极中引起电子注入的缺陷单元的存在。