-
公开(公告)号：US08451650B2
公开(公告)日：2013-05-28
申请号：US13524809
申请日：2012-06-15
IPC分类号： G11C11/24
CPC分类号： G11C11/401 , G11C11/405 , G11C11/408 , G11C11/409 , H01L27/0705 , H01L27/108 , H01L27/10802 , H01L29/66666 , H01L29/7841
摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。
-
2.发明申请公开(公告)号：US20120258577A1
公开(公告)日：2012-10-11
申请号：US13524809
申请日：2012-06-15
IPC分类号： H01L21/8239
CPC分类号： G11C11/401 , G11C11/405 , G11C11/408 , G11C11/409 , H01L27/0705 , H01L27/108 , H01L27/10802 , H01L29/66666 , H01L29/7841
摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。
-
公开(公告)号：US07557048B2
公开(公告)日：2009-07-07
申请号：US11472950
申请日：2006-06-21
IPC分类号： H01L21/31
CPC分类号： H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/823462 , H01L21/823481 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/785
摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.
摘要翻译： 本发明包括形成和/或钝化半导体结构的方法。 在具体方面，半导体衬底的各种氧化物可以通过将衬底的半导体材料暴露于富氘蒸汽来形成。 在其他方面，半导体结构通过在大于或等于350℃的温度下对该结构进行退火而钝化，同时将构造暴露于富氘化环境。
-
公开(公告)号：US06495900B1
公开(公告)日：2002-12-17
申请号：US08969208
申请日：1997-11-12
IPC分类号： H01L2900
CPC分类号： H01L29/66136 , H01L21/764 , H01L29/4983 , H01L29/4991
摘要： Structures and methods are disclosed for insulating a polysilicon gate adjacent to an electrically active region with a silicon base layer. A layer of silicon nitride having a thickness in a range from about 100 Å to about 150 Å is conformally deposited over the polysilicon gate. A layer of silicon dioxide is formed over the layer of silicon nitride on the polysilicon gate. The layer of silicon dioxide is subjected to a spacer etch to form spacers upon the layer of silicon nitride and on lateral sidewalls of the polysilicon gate. A portion of the layer of silicon nitride situated between the polysilicon gate and the spacer is removed by an etching process that is selective to silicon dioxide and to polysilicon. The etch forms a recess defined between the polysilicon gate and each respective spacer. A cover layer is formed to close an opening to the recess so as to enclose a void therein. Alternatively, the etch can be a series of selective etches that extends the recess into the silicon base layer, after which the silicon base layer is implanted so that the recess isolates electrically active areas in the silicon base layer. A void is then enclosed below the opening to the recess within the silicon base layer by a cover layer deposited non-conformally thereover.
摘要翻译： 公开了用于将具有硅基层的与电活性区相邻的多晶硅栅极绝缘的结构和方法。 在多晶硅栅极上共形沉积厚度在大约至大约的范围内的氮化硅层。 在多晶硅栅极上的氮化硅层上形成二氧化硅层。 对二氧化硅层进行间隔蚀刻以在氮化硅层和多晶硅栅极的侧壁上形成间隔物。 通过对二氧化硅和多晶硅有选择性的蚀刻工艺来去除位于多晶硅栅极和间隔物之间的氮化硅层的一部分。 蚀刻形成在多晶硅栅极和每个相应间隔物之间限定的凹部。 形成覆盖层以闭合到凹部的开口以便在其中包围空隙。 或者，蚀刻可以是将凹槽延伸到硅基层中的一系列选择性蚀刻，然后注入硅基层，使得凹陷隔离硅基层中的电活性区域。 然后，通过在其上非保形地沉积的覆盖层将空隙封闭在硅基底层内的开口下方的凹陷处。
-
公开(公告)号：US07919800B2
公开(公告)日：2011-04-05
申请号：US11711449
申请日：2007-02-26
IPC分类号： H01L27/108 , H01L29/94 , H01L27/088
CPC分类号： G11C11/401 , G11C11/405 , G11C11/408 , G11C11/409 , H01L27/0705 , H01L27/108 , H01L27/10802 , H01L29/66666 , H01L29/7841
摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有源区的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。
-
6.发明申请Capacitor-less volatile memory cell, device, system and method of making same 有权无电容易失性存储单元，器件，系统及其制造方法公开(公告)号：US20080205133A1
公开(公告)日：2008-08-28
申请号：US11711449
申请日：2007-02-26
IPC分类号： G11C11/34 , H01L21/8232
CPC分类号： G11C11/401 , G11C11/405 , G11C11/408 , G11C11/409 , H01L27/0705 , H01L27/108 , H01L27/10802 , H01L29/66666 , H01L29/7841
摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。
-
公开(公告)号：US07189662B2
公开(公告)日：2007-03-13
申请号：US10925793
申请日：2004-08-24
IPC分类号： H01L21/31
CPC分类号： H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/823462 , H01L21/823481 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/785
摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.
摘要翻译： 本发明包括形成和/或钝化半导体结构的方法。 在具体方面，半导体衬底的各种氧化物可以通过将衬底的半导体材料暴露于富氘蒸汽来形成。 在其他方面，半导体结构通过在大于或等于350℃的温度下对该结构进行退火而钝化，同时将构造暴露于富氘化环境。
-
公开(公告)号：US06190996B1
公开(公告)日：2001-02-20
申请号：US09365659
申请日：1999-08-02
IPC分类号： H01L2176
CPC分类号： H01L29/66136 , H01L21/764 , H01L29/4983 , H01L29/4991
摘要： Structures and methods are disclosed for insulating a polysilicon gate adjacent to an electrically active region with a silicon base layer. A layer of silicon nitride having a thickness in a range from about 100 Å to about 150 Å is conformally deposited over the polysilicon gate. A layer of silicon dioxide is formed over the layer of silicon nitride on the polysilicon gate. The layer of silicon dioxide is subjected to a spacer etch to form spacers upon the layer of silicon nitride and on lateral sidewalls of the polysilicon gate. A portion of the layer of silicon nitride situated between the polysilicon gate and the spacer is removed by an etching process that is selective to silicon dioxide and to polysilicon. The etch forms a recess defined between the polysilicon gate and each respective spacer. A cover layer is formed to close an opening to the recess so as to enclose a void therein. Alternatively, the etch can be a series of selective etches that extends the recess into the silicon base layer, after which the silicon base layer is implanted so that the recess isolate, electrically active areas in the silicon base layer. A void is then enclosed below the opening to the recess within the silicon base layer by a cover layer deposited non-conformally thereover.
摘要翻译： 公开了用于将具有硅基层的与电活性区相邻的多晶硅栅极绝缘的结构和方法。 在多晶硅栅极上共形沉积厚度在大约至大约的范围内的氮化硅层。 在多晶硅栅极上的氮化硅层上形成二氧化硅层。 对二氧化硅层进行间隔蚀刻以在氮化硅层和多晶硅栅极的侧壁上形成间隔物。 通过对二氧化硅和多晶硅有选择性的蚀刻工艺来去除位于多晶硅栅极和间隔物之间的氮化硅层的一部分。 蚀刻形成在多晶硅栅极和每个相应间隔物之间限定的凹部。 形成覆盖层以闭合到凹部的开口以便在其中包围空隙。 或者，蚀刻可以是将凹槽延伸到硅基层中的一系列选择性蚀刻，然后注入硅基层，使得凹槽隔离硅基层中的电活性区域。 然后，通过在其上非保形地沉积的覆盖层将空隙封闭在硅基底层内的开口下方的凹陷处。
-
公开(公告)号：US08203866B2
公开(公告)日：2012-06-19
申请号：US13073624
申请日：2011-03-28
IPC分类号： G11C11/24
CPC分类号： G11C11/401 , G11C11/405 , G11C11/408 , G11C11/409 , H01L27/0705 , H01L27/108 , H01L27/10802 , H01L29/66666 , H01L29/7841
摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。
-
10.发明申请公开(公告)号：US20110170364A1
公开(公告)日：2011-07-14
申请号：US13073624
申请日：2011-03-28
IPC分类号： G11C7/00 , H01L21/336
CPC分类号： G11C11/401 , G11C11/405 , G11C11/408 , G11C11/409 , H01L27/0705 , H01L27/108 , H01L27/10802 , H01L29/66666 , H01L29/7841
摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。
-
-
-
-
-
-
-
-
-
搜索结果
42 条记录 (耗时 0.019 秒)
