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公开(公告)号：US20130326251A1
公开(公告)日：2013-12-05
申请号：US13628000
申请日：2012-09-26
申请人： Fiyinfolu O. Adewale , Paul J. Costa , David R. Cox , Michael J. Giles , Steven I. Kuo , Nicholas W. Ruhter , Steven J. Sfarzo
发明人： Fiyinfolu O. Adewale , Paul J. Costa , David R. Cox , Michael J. Giles , Steven I. Kuo , Nicholas W. Ruhter , Steven J. Sfarzo
CPC分类号： G06F1/3253 , G06F1/266 , G06F1/3215 , G06F1/3234
摘要： A method and apparatus for recovering from a low power state in a computing system is disclosed. In one embodiment of the method, the computing system enters the low power state from a standard power state after an activity detector indicates a user controlled peripheral device connected to the computer system has been inactive for a period of time. To enter the low power state, the method disconnects the user controlled peripheral device from a host controller, while continuing to supply power to the user controlled peripheral device and shutting off power to the host controller. The method returns the computer system to the standard power state when the activity detector indicates the user controlled peripheral device has become active. To return to the standard power state, power is restored to the host controller and the user controlled peripheral device is reconnected to the host controller.
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公开(公告)号：US20110185208A1
公开(公告)日：2011-07-28
申请号：US12895702
申请日：2010-09-30
申请人： Derek Iwamoto , Steven J. Sfarzo , Ryan Schmidt , Derrick Carty , Keith Cox
发明人： Derek Iwamoto , Steven J. Sfarzo , Ryan Schmidt , Derrick Carty , Keith Cox
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G11C5/141 , G11C5/148 , G11C11/4074 , Y02D10/14 , Y02D50/20
摘要： A data processing system that uses memory power reduction in a sleep state. The system can include a volatile memory and at least one data input peripheral and a logic circuit that is configured to manage power consumption of the data processing system for a sleep of the system. The logic circuit can be coupled to the volatile memory and can be configured to turn off power to the volatile memory in response to an event, occurring during the sleep state, but to otherwise remain in the sleep state. The sleep state can be an ACPI complaint S3 sleep state in which the volatile memory, such as DRAM, is powered off after a period of user inactivity during the S3 sleep state.
摘要翻译： 在休眠状态下使用存储器功率降低的数据处理系统。 该系统可以包括易失性存储器和至少一个数据输入外围设备和逻辑电路，该逻辑电路被配置为管理数据处理系统对系统的睡眠的功耗。 逻辑电路可以耦合到易失性存储器，并且可以被配置为响应于在睡眠状态期间发生的事件而关闭到易失性存储器的电力，但是否则保持在睡眠状态。 休眠状态可以是ACMI投诉S3休眠状态，其中诸如DRAM之类的易失性存储器在S3睡眠状态期间的用户不活动期间之后被关闭。
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公开(公告)号：US20090174462A1
公开(公告)日：2009-07-09
申请号：US12242904
申请日：2008-09-30
CPC分类号： G06F1/1658 , G06F1/1616 , G06F3/044 , H03K17/96 , H03K2217/96015 , H03K2217/960755 , Y10T29/49002
摘要： Electronic devices may be provided with one or more input components and one or more circuit boards. An input component may include sensor circuitry supported by a first circuit board and controller circuitry supported by a second circuit board. In other embodiments, the sensor circuitry may be coupled to a first portion of a first surface of a circuit board and the controller circuitry may be coupled to a second portion of the first surface of the same circuit board. The input component may be a multi-touch input component, such as a multi-touch trackpad.
摘要翻译： 电子设备可以设置有一个或多个输入组件和一个或多个电路板。 输入组件可以包括由第一电路板支持的传感器电路和由第二电路板支持的控制器电路。 在其他实施例中，传感器电路可以耦合到电路板的第一表面的第一部分，并且控制器电路可以耦合到同一电路板的第一表面的第二部分。 输入组件可以是多触摸输入组件，例如多点触控式触控板。
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4.发明申请SYSTEMS AND METHODS FOR MONITORING AND RESPONDING TO FORCES INFLUENCING A BATTERY 审中-公开用于监测和响应影响电池的系统和方法公开(公告)号：US20090169977A1
公开(公告)日：2009-07-02
申请号：US12242898
申请日：2008-09-30
CPC分类号： H01M6/5044 , H01M10/052 , H01M10/48
摘要： Systems and methods for monitoring and responding to forces influencing batteries of electronic devices are provided.
摘要翻译： 提供了用于监测和响应影响电子设备的电池的力的系统和方法。
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