公开(公告)号：US5899741A

公开(公告)日：1999-05-04

申请号：US40432

申请日：1998-03-18

Applicant: Fouriers Tseng ,  Peng-Cheng Chou

Inventor： Fouriers Tseng ,  Peng-Cheng Chou

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76862 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76861 ,  H01L21/76877

Abstract: A new method of forming an amorphous silicon glue layer in the formation of a contact is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. An amorphous silicon layer is deposited overlying the insulating layer and within the opening. Ions are implanted into the amorphous silicon layer whereby grain sizes within the amorphous silicon layer are reduced. Native oxide on the surface of the amorphous silicon layer is removed. A titanium/titanium nitride layer is deposited overlying the amorphous silicon layer. A metal layer is deposited overlying the titanium/titanium nitride layer and filling the opening. The substrate is annealed whereby the titanium layer reacts with the amorphous silicon layer and the silicon semiconductor substrate to form titanium silicide. The metal layer is etched back or patterned to complete metallization in the fabrication of an integrated circuit device.

Abstract translation: 描述了在形成接触时形成非晶硅胶层的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 绝缘层沉积在半导体器件结构上。 通过绝缘层蚀刻开口以接触半导体器件结构之一。 非晶硅层沉积在绝缘层上并且在开口内。 将离子注入到非晶硅层中，由此减小非晶硅层内的晶粒尺寸。 去除非晶硅层表面上的天然氧化物。 覆盖在非晶硅层上的钛/氮化钛层被沉积。 沉积覆盖在钛/氮化钛层上并填充开口的金属层。 将衬底退火，由此钛层与非晶硅层和硅半导体衬底反应形成硅化钛。 金属层被回蚀或图案化以在集成电路器件的制造中完成金属化。

公开(公告)号：US06395580B1

公开(公告)日：2002-05-28

申请号：US09450143

申请日：1999-11-29

Applicant: Fouriers Tseng

Inventor： Fouriers Tseng

IPC: H01L2144

CPC classification number: G01R31/2886 ,  G01N1/32 ,  G01R31/311 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A method for conducting a backside failure analysis on a ball grid array (BGA) package that does not require a chemical etching step is described. In the method, a substrate can first be removed mechanically from the BGA package to expose a plastic encapsulated IC chip. The molding compound on the backside of the IC chip can then be removed by a mechanical method such as polishing or preferably, chemical mechanical polishing. Simultaneously with the exposure of the backside of the IC chip, the ends of a plurality of bonding wires which are connected to the bond pads on the top surface of the IC chip is also exposed. A plurality of probe needles or a bonder can then be used to make electrical contact with the ends of the bonding wires such that signals may be fed into the IC chip for conducting a failure analysis. The present invention novel method provides the advantage that the observation for the failure sites and the electrical connections to the IC chip can all be conducted on the same surface of the package and thus be carried out at low cost and in a simplified manner.

Abstract translation: 描述了对不需要化学蚀刻步骤的球栅阵列（BGA）封装进行背面故障分析的方法。 在该方法中，可以首先从BGA封装机械地去除衬底以暴露塑料封装的IC芯片。 然后可以通过诸如抛光或优选化学机械抛光的机械方法去除IC芯片背面上的模塑料。 与IC芯片的背面曝光同时，与IC芯片的上表面上的接合焊盘连接的多根接合线的端部也露出。 然后可以使用多个探针或接合器与接合线的端部进行电接触，使得可以将信号馈送到IC芯片中进行故障分析。 本发明新颖的方法具有以下优点：对IC芯片的故障点和电连接的观察都可以在封装的相同表面上进行，从而以低成本和简化的方式进行。

公开(公告)号：US06407564B1

公开(公告)日：2002-06-18

申请号：US09368199

申请日：1999-08-04

Applicant: Fouriers Tseng

Inventor： Fouriers Tseng

IPC: G01R302

CPC classification number: G01R1/0483

Abstract: An universal ball grid array (BGA) test board for performing a failure analysis on any size IC chips and a method for performing such analysis are disclosed. In the universal BGA test board, an electrically insulating material is used as a substrate with a rectangular opening provided at a center. A plurality of spaced-apart conductive lines are provided surrounding and adjacent to the center opening for use as ground and power supply respectively. A multiplicity of conductive leads, a multiplicity of ball pads are then provided on the surface of the substrate with a multiplicity of conductive traces connecting thereinbetween such that one conductive lead is connected to one ball pad. The test method can be easily conducted by first wire bonding the conductive leads to the bond pads on the IC chip and then contacting the ball pads with probe needles for feeding in test signals into the IC chip. Defects are shown as hot spots in a liquid crystal material that is coated on the top surface of the IC chip.

Abstract translation: 公开了用于对任何尺寸的IC芯片执行故障分析的通用球栅阵列（BGA）测试板和用于执行这种分析的方法。 在通用BGA测试板中，使用电绝缘材料作为在中心设置有矩形开口的基板。 围绕和邻近中心开口设置多个间隔开的导电线，分别用作接地和电源。 多个导电引线，然后在基片的表面上提供多个球垫，其中连接有多个导电迹线，使得一个导电引线连接到一个球垫。 通过首先将导线引线接合到IC芯片上的接合焊盘，然后使球垫与探针接触，将测试信号馈送到IC芯片中，可以容易地进行测试方法。 缺陷在被涂覆在IC芯片的顶表面上的液晶材料中显示为热点。

公开(公告)号：US06586312B1

公开(公告)日：2003-07-01

申请号：US09056985

申请日：1998-04-08

Applicant: Pin Hsiang Chin ,  Fouriers Tseng

Inventor： Pin Hsiang Chin ,  Fouriers Tseng

IPC: H01L2120

CPC classification number: H01L28/87 ,  H01L21/31612 ,  H01L21/31625 ,  H01L27/10814 ,  H01L27/10855

Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by first alternatingly depositing layers of BPTEOS oxide and PETEOS oxide onto a semiconductor substrate and then forming a contact hole through the insulating layers utilizing a wet etchant that has high selectivity for the PETEOS oxide layers such that a zig-zag surface is formed in the contact hole and subsequently a capacitor that has improved charge storage capacity. The present invention novel method can be used to form any type of stacked capacitors, for instance, a stacked capacitor, a fin-type stacked capacitor, a crown-type stacked capacitor, etc.

Abstract translation: 本发明公开了一种用于形成DRAM电容器的方法，该方法通过首先在半导体衬底上交替沉积BPTEOS氧化物和PETEOS氧化物层，然后利用具有高选择性的湿蚀刻剂在绝缘层上形成接触孔，从而改善电荷存储容量 对于PETEOS氧化物层，使得在接触孔中形成锯齿形表面，随后形成具有改善的电荷存储容量的电容器。 本发明的新颖方法可用于形成任何类型的叠层电容器，例如叠层电容器，鳍式叠层电容器，冠型堆叠电容器等。

公开(公告)号：US06397373B1

公开(公告)日：2002-05-28

申请号：US09351242

申请日：1999-07-12

Applicant: Fouriers Tseng ,  Chin-Kai Liu

Inventor： Fouriers Tseng ,  Chin-Kai Liu

IPC: G06F1750

CPC classification number: G06F17/5081

Abstract: A method/system is provided for performing a design review checking operation and analyzing the resultant data. Perform a DRC operation describing chip features and generating flags for violation sites including patterns and paths. Execute pattern analysis and grade classification steps for the violation sites. Generate a vector array for each chip feature for each of the violation sites. Compare the vector arrays to determine whether degrees of similarity of geometries of chip features of violation sites meet one of a set of criteria. Classify the violation sites into classes with similar criteria. Select representative arrays from each class of violation sites to provide an output. Calculate distance from a violation site from the origin in a two-dimensional array. Give a grade to each vector array to indicate the level of seriousness of the rule violation by the site. Use a layout viewer to view the error flags generated by pattern analysis and grade classification steps.

Abstract translation: 提供了一种用于执行设计审查检查操作并分析所得数据的方法/系统。 执行描述芯片功能的DRC操作，并为违规站点生成标志，包括模式和路径。 对违规网站执行模式分析和等级分类步骤。 为每个违规站点的每个芯片功能生成一个矢量数组。 比较矢量数组以确定违规站点的芯片特征的几何的相似度是否满足一组标准之一。 将违规网站划分为类似标准的类。 从每个类别的违规站点中选择代表性的数组以提供输出。 从二维阵列中计算违规站点与原点的距离。 为每个矢量数组提供一个等级，以指示站点违规规则的严重程度。 使用布局查看器来查看由模式分析和成绩分类步骤生成的错误标志。

公开(公告)号：US06412104B1

公开(公告)日：2002-06-25

申请号：US09240849

申请日：1999-02-01

Applicant: Fouriers Tseng

Inventor： Fouriers Tseng

IPC: G06F9445

CPC classification number: G01R31/31705 ,  G01R31/319

Abstract: An integrated circuit debugging system is provided for debugging the integrated circuits with bi-directional terminals is disclosed. The system includes clock unit for providing clocks, and address generating unit for generating address responsive to the provided clock. An I/O control memory is used to store pin status of an integrated circuit under test corresponding to each of the generated address; and a timing diagram memory is used to store fitting value of the integrated circuit. Moreover, the system includes an I/O manipulating unit for directing signal into and out of the integrated circuit according to the stored pin status of the I/O control memory, and for comparing the signal out of the integrated circuit under test and the fitting value from the timing diagram memory. Further, feedback control unit is configured to control the address generation of the address generating unit.

Abstract translation: 公开了一种集成电路调试系统，用于对具有双向端子的集成电路进行调试。 该系统包括用于提供时钟的时钟单元，以及响应于所提供的时钟产生地址的地址生成单元。 I / O控制存储器用于存储与每个生成的地址相对应的被测集成电路的引脚状态; 并且使用时序图存储器来存储集成电路的拟合值。 此外，该系统包括I / O操作单元，用于根据存储的I / O控制存储器的引脚状态将信号引入和流出集成电路，并且用于将被测集成电路中的信号与拟合 值从时序图存储器。 此外，反馈控制单元被配置为控制地址生成单元的地址生成。

公开(公告)号：US06405359B1

公开(公告)日：2002-06-11

申请号：US09412206

申请日：1999-10-05

Applicant: Fouriers Tseng ,  Thomas Hung

Inventor： Fouriers Tseng ,  Thomas Hung

IPC: G06F1750

CPC classification number: G01R31/311

Abstract: A method for conducting backside failure analysis on a wafer that only requires simple bias conditions to be fed into defective IC dies and a wafer test specimen which enables such test are disclosed. In the method, a wafer can be first provided that contains at least one defective IC die in an active (or front) surface, at least two conductive metal strips formed of a metal foil are then adhesively bonded to the active surface of the wafer juxtaposed to the at least one defective IC die. At least two lead wires are then bonded by a wire bonding technique between the at least two conductive metal strips and at least two bond pads on the defective IC die for establishing electrical communication therein between. A bias voltage such as a VCC signal or a clock signal can then be fed to the defective IC die through the at least two conductive metal strips, while the defect being observed from the backside of the wafer with an optical detector. The present invention novel method and the wafer test specimen enable the method to be executed at a relatively low cost and a shortened analysis time since a complete wafer can be tested without first been severed and packaged into IC chips as normally required in conventional test methods. Furthermore, the present invention novel test method can be executed on selected defective IC dies on a wafer without disturbing, or damaging other good dies.

Abstract translation: 公开了一种用于在晶片上进行背面故障分析的方法，其仅需要将简单的偏置条件馈送到有缺陷的IC管芯中，并且公开了能够进行这种测试的晶片测试样本。 在该方法中，可以首先提供在活性（或前）表面中包含至少一个有缺陷的IC裸片的晶片，然后将至少两个由金属箔形成的导电金属条粘合到晶片的有源表面并置 至少一个有缺陷的IC芯片。 然后通过引线键合技术在至少两个导电金属条和有缺陷的IC管芯上的​​至少两个接合焊盘之间至少两个引线接合，以在其间建立电连通。 然后可以通过至少两个导电金属条将诸如VCC信号或时钟信号的偏置电压馈送到有缺陷的IC管芯，同时用光学检测器从晶片的背面观察到缺陷。 本发明的新颖方法和晶片试样使得该方法能够以相对较低的成本和缩短的分析时间执行，因为可以测试完整的晶片，而无需先将其切割并封装成IC芯片，这在常规测试方法中是常规要求。 此外，本发明的新颖的测试方法可以在晶片上的选定的有缺陷的IC芯片上执行，而不会干扰或损坏其他良好的裸片。

公开(公告)号：US06252227B1

公开(公告)日：2001-06-26

申请号：US09174653

申请日：1998-10-19

Applicant: Fouriers Tseng ,  Mei Fun Chen ,  At Chuan Chen ,  Huey Ling Chen

Inventor： Fouriers Tseng ,  Mei Fun Chen ,  At Chuan Chen ,  Huey Ling Chen

IPC: G01N2300

CPC classification number: G01N23/04

Abstract: An improved method for sectioning a semiconductor wafer using a focused ion beam (FIB) apparatus permits a clearer image of the site of the cut to be formed from secondary electrons produced by the beam. The clearer image helps the operator of the FIB apparatus to make a more accurate cut. Before the FIB cut is made, a laser is used to cut into the wafer to expose the lowermost layer of silicon dioxide. This oxide and any oxide splatters from the laser cut are then removed with an oxide etcher. The FIB cut can then be made without splattering silicon dioxide over the area being viewed. A low beam current is used for the FIB cut.

Abstract translation: 使用聚焦离子束（FIB）装置对半导体晶片进行切片的改进方法允许由束产生的二次电子形成切割部位的更清晰的图像。 更清晰的图像有助于FIB设备的操作者进行更精确的切割。 在制造FIB切割之前，使用激光切割成晶片以暴露最底层的二氧化硅。 然后用氧化物蚀刻器去除激光切割的氧化物和任何氧化物飞溅物。 然后可以在所观察的区域上形成FIB切割，而不会溅射二氧化硅。 短波束电流用于FIB切割。