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公开(公告)号：US07760085B2
公开(公告)日：2010-07-20
申请号：US11938315
申请日：2007-11-12
申请人： Francesco Lertora , Daniele Grosso , Giuseppe Oriana , Luca Noli
发明人： Francesco Lertora , Daniele Grosso , Giuseppe Oriana , Luca Noli
IPC分类号： G08B1/08
CPC分类号： B60K15/04 , B60K15/0406 , B60K2015/03197 , B60K2015/03361 , B60K2015/03434 , B60K2015/0493 , G01F23/0076
摘要： A monitoring apparatus for tanks and the like, comprising detecting means (4; 506) to detect the filling level of a tank, detecting means (5, 106; 206) to detect the opened and closed states of opening/closing means (6) of said tank, and gathering and processing means (106) to gather and process the detected data, characterized in that said processing means (106) are integrated with an RFID unit (116) which can communicate said data with at least one appropriate remote transceiver unit (7).
摘要翻译： 一种用于罐等的监视装置，包括检测装置的检测装置（4; 506），用于检测打开/关闭装置（6）的打开和关闭状态的检测装置（5,106; 206） 以及收集和处理装置（106）以收集和处理检测到的数据，其特征在于，所述处理装置（106）与RFID单元（116）集成，RFID单元可将数据与至少一个适当的远程收发器 单位（7）。
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2.发明申请INTEGRATED SOLUTION FOR SENSOR INTERFACE FOR MONITORING THE ENVIRONMENTAL PARAMETERS BY MEANS OF RFID TECHNOLOGIES 失效用于传感器接口的集成解决方案，用于通过RFID技术监测环境参数公开(公告)号：US20100060449A1
公开(公告)日：2010-03-11
申请号：US12516804
申请日：2007-11-29
IPC分类号： G08B1/08
CPC分类号： G01V15/00 , G06K19/0717 , G06K19/077
摘要： Integrated device comprising: a microprocessor unit (1) which is interfaced to a program memory unit (2), a data memory unit (3), one or more integrated sensors (11), one or more external sensors (12) which may be either digitally or analogically interfaced, an RFID unit (7, 107), an RTC (Real Time Clock) synchronization module (5, 105) which can also control power supply means (13), said device further comprising a power supply and consumption management logic.
摘要翻译： 一种集成装置，包括：与程序存储单元（2）相连的微处理器单元（1），数据存储单元（3），一个或多个集成传感器（11），一个或多个外部传感器（12） 数字或类比地接口的RFID单元（7,107），还可以控制电源装置（13）的RTC（实时时钟）同步模块（5,105），所述设备还包括电源和消耗管理 逻辑。
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3.发明授权Integrated solution for sensor interface for monitoring the environmental parameters by means of RFID technologies 失效用于通过RFID技术监测环境参数的传感器接口的集成解决方案公开(公告)号：US08035512B2
公开(公告)日：2011-10-11
申请号：US12516804
申请日：2007-11-29
IPC分类号： G08B1/08
CPC分类号： G01V15/00 , G06K19/0717 , G06K19/077
摘要： Integrated device comprising: a microprocessor unit (1) which is interfaced to a program memory unit (2), a data memory unit (3), one or more integrated sensors (11), one or more external sensors (12) which may be either digitally or analogically interfaced, an RFID unit (7, 107), an RTC (Real Time Clock) synchronization module (5, 105) which can also control power supply means (13), said device further comprising a power supply and consumption management logic.
摘要翻译： 一种集成装置，包括：与程序存储单元（2）相连的微处理器单元（1），数据存储单元（3），一个或多个集成传感器（11），一个或多个外部传感器（12） 数字或类比地接口的RFID单元（7,107），还可以控制电源装置（13）的RTC（实时时钟）同步模块（5,105），所述设备还包括电源和消耗管理 逻辑。
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公开(公告)号：US07886168B2
公开(公告)日：2011-02-08
申请号：US11856018
申请日：2007-09-15
摘要： Taught is a detection device for detecting impacts and the like, comprising an integrated microcontroller (1) which includes an RFID interface (101) and a non-volatile memory (201), the integrated microcontroller (1) being interfaced with at least one suitable sensing means (2) through a suitable digital interface (102), the integrated microcontroller (1) being provided with a power management logic (301) to manage operation modes of the detection device, power consumption of the sensing means (2) being managed by the power management logic (301).
摘要翻译： 教授是用于检测影响等的检测装置，包括集成微控制器（1），其包括RFID接口（101）和非易失性存储器（201），所述集成微控制器（1）与至少一个适当的 感测装置（2）通过适当的数字接口（102），集成微控制器（1）设置有电力管理逻辑（301）以管理检测装置的操作模式，管理感测装置（2）的功耗 通过电源管理逻辑（301）。
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5.发明授权Architecture for dynamically reconfigurable system-on-chip arrangements, related methods and computer program product 有权用于动态重新配置系统级芯片布局的架构，相关方法和计算机程序产品公开(公告)号：US07818163B2
公开(公告)日：2010-10-19
申请号：US11402281
申请日：2006-04-11
IPC分类号： G06F9/455
CPC分类号： G06F15/7867
摘要： A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.
摘要翻译： 具有可能与处理器组合的多个可重新配置的门阵列器件以及可配置的片上系统的芯片上系统布置，其连接门阵列器件以使得布置可升级。 该装置本身通过在门阵列的一个装置中映射一组处理模块来操作，并且将多个门阵列装置中的另一装置配置为具有存储有用于控制处理的操作的软件代码部分的微控制器 存储在多个设备中的模块。 因此，该布置适于例如处理不同的计算粒度级别。
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6.发明申请Architecture for dynamically reconfigurable system-on-chip arrangements, related methods and computer program product 有权用于动态重新配置系统级芯片布局的架构，相关方法和计算机程序产品公开(公告)号：US20070088537A1
公开(公告)日：2007-04-19
申请号：US11402281
申请日：2006-04-11
IPC分类号： G06F9/455
CPC分类号： G06F15/7867
摘要： A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.
摘要翻译： 具有可能与处理器组合的多个可重新配置的门阵列器件以及可配置的片上系统的芯片上系统布置，其连接门阵列器件以使得布置可升级。 该装置本身通过在门阵列的一个装置中映射一组处理模块来操作，并且将多个门阵列装置中的另一装置配置为具有存储有用于控制处理的操作的软件代码部分的微控制器 存储在多个设备中的模块。 因此，该布置适于例如处理不同的计算粒度级别。
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7.发明授权公开(公告)号：US07360068B2
公开(公告)日：2008-04-15
申请号：US10768401
申请日：2004-01-30
IPC分类号： G06F13/00
CPC分类号： G06F15/7867 , G11C16/30 , Y02D10/12 , Y02D10/13
摘要： A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field programmable gate array (FPGA) port. The reconfigurable processing unit further includes a direct memory access (DMA) channel, and an S-RAM embedded FPGA for FPGA reconfigurations. The S-RAM embedded FPGA has an FPGA programming interface connected to the FPGA port of the Flash memory through the DMA channel. The microprocessor, the embedded Flash memory, the DMA channel and the S-RAM embedded FPGA are integrated as a single chip.
摘要翻译： 动态可重构处理单元包括微处理器和用于代码，数据和比特流的非易失性存储的嵌入式闪存。 嵌入式闪存包括现场可编程门阵列（FPGA）端口。 可重构处理单元还包括直接存储器访问（DMA）通道和用于FPGA重新配置的S-RAM嵌入式FPGA。 S-RAM嵌入式FPGA具有通过DMA通道连接到闪存的FPGA端口的FPGA编程接口。 微处理器，嵌入式闪存，DMA通道和S-RAM嵌入式FPGA集成为单芯片。
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