公开(公告)号：US08492225B2

公开(公告)日：2013-07-23

申请号：US12938589

申请日：2010-11-03

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: H01L21/336

CPC classification number: H01L27/0629 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.

Abstract translation: 一种电压转换器的方法和结构，包括与沟槽FET集成的沟槽场效应晶体管（FET）和沟槽保护肖特基二极管。 在一个实施例中，电压转换器可以包括横向FET，沟槽FET和与沟槽FET集成的沟槽保护肖特基二极管。 形成电压转换器的方法可以包括使用诸如多晶硅层的单个导电层形成沟槽FET栅极，沟槽保护肖特基二极管栅极和横向FET栅极。

公开(公告)号：US20110121387A1

公开(公告)日：2011-05-26

申请号：US12770074

申请日：2010-04-29

Applicant: Francois Hebert ,  Dev Alok Girdhar

Inventor： Francois Hebert ,  Dev Alok Girdhar

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66727 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/872

Abstract: A plurality of transistor cells, each of which can include a transistor P-body region and a Schottky diode, wherein the transistor P-body region can be formed below the Schottky diode to provide a semiconductor device having desirable electrical characteristics.

Abstract translation: 多个晶体管单元，其中每个晶体管单元可以包括晶体管P体区域和肖特基二极管，其中晶体管P体区域可以形成在肖特基二极管下方，以提供具有所需电气特性的半导体器件。

公开(公告)号：US20110156682A1

公开(公告)日：2011-06-30

申请号：US12898664

申请日：2010-10-05

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: H02M3/156 ,  H01L27/07 ,  H01L21/74

CPC classification number: H01L27/0629 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/872 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device such as a voltage converter includes a circuit stage such as an output stage having a high side device and a low side device which can be formed on a single die (i.e., a “PowerDie”) and connected to each other through a semiconductor substrate, and further includes a Schottky diode integrated with at least one of the low side device and the high side device. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. Various embodiments of the Schottky diode can provide Schottky protection and, additionally JFET protection for the Schottky device.

Abstract translation: 诸如电压转换器的半导体器件包括诸如具有高侧器件的输出级的电路级和可以形成在单个管芯（即，“PowerDie”）上并通过一个管芯彼此连接的低侧器件的电路级 半导体衬底，并且还包括与低侧器件和高侧器件中的至少一个集成的肖特基二极管。 高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。 因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。 电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。 肖特基二极管的各种实施例可以提供肖特基保护和另外用于肖特基器件的JFET保护。

公开(公告)号：US08362555B2

公开(公告)日：2013-01-29

申请号：US12796178

申请日：2010-06-08

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: H01L29/66

CPC classification number: H01L27/088

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract translation: 电压转换器包括具有高侧器件和低侧器件的输出电路，其可以形成在单个管芯（即PowerDie）上，并通过半导体衬底相互连接。 高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。 因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。 电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。

公开(公告)号：US20110156679A1

公开(公告)日：2011-06-30

申请号：US12938589

申请日：2010-11-03

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: H01L27/06 ,  H01L21/336 ,  G05F1/618

CPC classification number: H01L27/0629 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.

Abstract translation: 一种电压转换器的方法和结构，包括与沟槽FET集成的沟槽场效应晶体管（FET）和沟槽保护肖特基二极管。 在一个实施例中，电压转换器可以包括横向FET，沟槽FET和与沟槽FET集成的沟槽保护肖特基二极管。 形成电压转换器的方法可以包括使用诸如多晶硅层的单个导电层形成沟槽FET栅极，沟槽保护肖特基二极管栅极和横向FET栅极。

公开(公告)号：US20110121808A1

公开(公告)日：2011-05-26

申请号：US12796178

申请日：2010-06-08

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: G05F3/02 ,  H01L21/8234

CPC classification number: H01L27/088

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract translation: 电压转换器包括具有高侧器件的输出电路和可以形成在单个管芯（即“PowerDie”）上并通过半导体衬底相互连接的低侧器件。 高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。 因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。 电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。

公开(公告)号：US08647971B2

公开(公告)日：2014-02-11

申请号：US13356624

申请日：2012-01-23

Applicant: Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

Inventor： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7833

Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

Abstract translation: 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。

公开(公告)号：US20100314708A1

公开(公告)日：2010-12-16

申请号：US12868346

申请日：2010-08-25

Applicant: Dev Alok Girdhar ,  Michael David Church

Inventor： Dev Alok Girdhar ,  Michael David Church

IPC: H01L29/872

CPC classification number: H01L29/66143 ,  H01L27/0629 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/872

Abstract: A junction barrier Schottky diode has an N-type well having a surface and a first peak impurity concentration; a P-type anode region in the surface of the well, and having a second peak impurity concentration; an N-type cathode contact region in the surface of the well and laterally spaced from a first wall of the anode region, and having a third peak impurity concentration; and a first N-type region in the surface of the well and laterally spaced from a second wall of the anode region, and having a fourth impurity concentration. The center of the spaced region between the first N-type region and the second wall of the anode region has a fifth peak impurity concentration. An ohmic contact is made to the anode region and cathode contact region, and a Schottky contact is made to the first N-type region. The first and fifth peak impurity concentrations are less than the fourth peak impurity concentration, and the fourth peak impurity concentration is less that the second and third peak impurity concentrations.

Abstract translation: 接合势垒肖特基二极管具有具有表面和第一峰值杂质浓度的N型阱; 阱的表面中的P型阳极区，具有第二峰杂质浓度; 在所述阱的表面中的N型阴极接触区域，并且与所述阳极区域的第一壁横向间隔开，并且具有第三峰值杂质浓度; 以及在所述阱的表面中的第一N型区域，并且与所述阳极区域的第二壁横向间隔开，并且具有第四杂质浓度。 阳极区域的第一N型区域和第二壁之间的间隔区域的中心具有第五峰值杂质浓度。 对阳极区域和阴极接触区域进行欧姆接触，并且对第一N型区域进行肖特基接触。 第一和第五峰杂质浓度小于第四峰杂质浓度，第四峰杂质浓度小于第二和第三峰杂质浓度。

公开(公告)号：US20090096019A1

公开(公告)日：2009-04-16

申请号：US12243253

申请日：2008-10-01

Applicant: Dev Alok Girdhar ,  Timothy Donald Henson

Inventor： Dev Alok Girdhar ,  Timothy Donald Henson

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/76

Abstract: A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench.

Abstract translation: 一种功率半导体器件，其包括源极电极和与源极场电极的相应侧相邻的至少一个绝缘栅电极，源极场电极和栅电极设置在公共沟槽中。

公开(公告)号：US20120122308A1

公开(公告)日：2012-05-17

申请号：US13356624

申请日：2012-01-23

Applicant: Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

Inventor： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

IPC: H01L21/8222

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7833

Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

Abstract translation: 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。