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    Debugging for multiple errors in a microprocessor environment
    2.
    发明授权
    Debugging for multiple errors in a microprocessor environment 有权
    在微处理器环境中调试多个错误

    公开(公告)号：US08095821B2

    公开(公告)日：2012-01-10

    申请号：US12405418

    申请日：2009-03-17

    申请人： Ulrich Mayer ,  Timothy John Slegel ,  Chung-Lung Kevin Shum ,  Frank Lehnert ,  Guenter Gerwig

    发明人： Ulrich Mayer ,  Timothy John Slegel ,  Chung-Lung Kevin Shum ,  Frank Lehnert ,  Guenter Gerwig

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1407 ,  G06F9/3863 ,  G06F9/3865 ,  G06F11/0721 ,  G06F11/076 ,  G06F11/0772

    摘要： A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging.

    摘要翻译： 已经教导了一种新的方法和装置，用于存储由初始和随后的错误发生产生的用于调试的错误信息。 在本发明中，使用具有多个位范围的寄存器来存储错误信息。 第一个比特范围被分配给初始的错误信息。 如果错误总数超过寄存器的容量，则最后一个错误将保留在最后一个位范围内。 这样，宝贵的初始错误信息（以及最后一个错误信息）将可用于调试。

    Branch target buffer preload table
    5.
    发明授权
    Branch target buffer preload table 有权

    公开(公告)号：US09235419B2

    公开(公告)日：2016-01-12

    申请号：US13492997

    申请日：2012-06-11

    申请人： James J. Bonanno ,  Ulrich Mayer ,  Brian R. Prasky

    发明人： James J. Bonanno ,  Ulrich Mayer ,  Brian R. Prasky

    IPC分类号： G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/3806

    摘要： Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry.

    INSTRUCTION FILTERING
    6.
    发明申请
    INSTRUCTION FILTERING 有权
    指令过滤

    公开(公告)号：US20130339683A1

    公开(公告)日：2013-12-19

    申请号：US13523170

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

    摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

    摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

    UV irradiance monitoring in semiconductor processing using a temperature dependent signal
    7.
    发明授权
    UV irradiance monitoring in semiconductor processing using a temperature dependent signal 有权
    使用温度依赖信号的半导体处理中的紫外线辐照度监测

    公开(公告)号：US08518720B2

    公开(公告)日：2013-08-27

    申请号：US12854995

    申请日：2010-08-12

    申请人： Ulrich Mayer ,  Thorsten Schepers

    发明人： Ulrich Mayer ,  Thorsten Schepers

    IPC分类号： H01L21/66

    CPC分类号： H01L21/3105 ,  H01L21/67115 ,  H01L21/67248

    摘要： In a UV process tool for semiconductor processing, a temperature-dependent signal may be used as a monitor signal for determining the momentary irradiance of the UV radiation source. Consequently, a fast and reliable monitoring and/or controlling of the irradiance of UV process tools may be accomplished.

    摘要翻译： 在用于半导体处理的UV处理工具中，可以使用温度依赖信号作为用于确定UV辐射源的瞬时辐照度的监视信号。 因此，可以实现对UV处理工具的辐照度的快速和可靠的监测和/或控制。

    Multiprocessor electronic circuit including a plurality of processors and electronic data processing system
    8.
    发明授权
    Multiprocessor electronic circuit including a plurality of processors and electronic data processing system 有权
    多处理器电子电路包括多个处理器和电子数据处理系统

    公开(公告)号：US08135960B2

    公开(公告)日：2012-03-13

    申请号：US12248549

    申请日：2008-10-09

    申请人： Thomas Koehler ,  Thomas Fuchs ,  Ulrich Mayer ,  Chung-Lung Kevin Shum ,  Scott Barnett Swaney

    发明人： Thomas Koehler ,  Thomas Fuchs ,  Ulrich Mayer ,  Chung-Lung Kevin Shum ,  Scott Barnett Swaney

    IPC分类号： G06F12/14

    CPC分类号： G06F21/72

    摘要： A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.

    摘要翻译： 公开了一种包括这种电路的多处理器电子电路和电子数据处理系统，用于降低具有加密功能的多处理器系统的功耗和芯片面积消耗。 在一个实施例中，多处理器电子电路包括多个处理器，包括多个输入/输出缓冲器对和两个加密引擎，密码引擎和哈希引擎以及相关控制逻辑的单个密码处理单元。