公开(公告)号：US20100184389A1

公开(公告)日：2010-07-22

申请号：US12063425

申请日：2005-08-09

申请人： Frederic Fraysse ,  Gilles Montoriol ,  Didier Salle

发明人： Frederic Fraysse ,  Gilles Montoriol ,  Didier Salle

IPC分类号： H04B1/02

CPC分类号： H04B1/04

摘要： A wireless communication unit (100) comprises a transmitter (120) arranged to transmit an envelope modulated signal. The transmitter (120) comprises a radio frequency power amplifier (124) operably coupled to a logarithmic detector (210, 310) and a bias control circuit (126) arranged to set a direct current bias level of the radio frequency power amplifier (124) via a bias signal. The logarithmic detector (210, 310) is arranged to detect the envelope modulated signal and provide the detected envelope modulated signal to the bias control circuit such that the bias signal applied to the radio frequency power amplifier (124) comprises both a direct current and a low frequency component based on the detected envelope modulated signal. In this manner, the present invention supports a tradeoff of linearity for additional efficiency, as well as providing more margin on adjacent channel power levels, whilst maintaining a good overall power added efficiency.

摘要翻译： 无线通信单元（100）包括被布置为发射包络调制信号的发射机（120）。 发射机（120）包括可操作地耦合到对数检测器（210,310）的射频功率放大器（124）和被布置成设置射频功率放大器（124）的直流偏置电平的偏置控制电路（126） 通过偏置信号。 对数检测器（210,310）被布置成检测包络调制信号，并将检测到的包络调制信号提供给偏置控制电路，使得施加到射频功率放大器（124）的偏置信号包括直流电和 基于检测到的包络调制信号的低频分量。 以这种方式，本发明支持对于附加效率的线性的折衷，并且在相邻信道功率电平上提供更多的余量，同时保持良好的整体功率附加效率。

公开(公告)号：US20110285575A1

公开(公告)日：2011-11-24

申请号：US13145122

申请日：2009-02-13

申请人： Christophe Landez ,  Hugues Beaulaton ,  Thierry Cassagnes ,  Stephane Colomines ,  Robert G. Gach ,  Akbar Ghazinour ,  Hao Li ,  Gilles Montoriol ,  Didier Salle ,  Pierre Savary

发明人： Christophe Landez ,  Hugues Beaulaton ,  Thierry Cassagnes ,  Stephane Colomines ,  Robert G. Gach ,  Akbar Ghazinour ,  Hao Li ,  Gilles Montoriol ,  Didier Salle ,  Pierre Savary

IPC分类号： G01S13/02

CPC分类号： G01S7/35 ,  G01S7/032 ,  G01S13/34 ,  G01S13/931 ,  G01S2013/9325 ,  H03C3/0925 ,  H03L7/1976

摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

摘要翻译： 集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。 频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑 并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

公开(公告)号：US08654006B2

公开(公告)日：2014-02-18

申请号：US13145122

申请日：2009-02-13

申请人： Christophe Landez ,  Hugues Beaulaton ,  Thierry Cassagnes ,  Stephane Colomines ,  Robert G. Gach ,  Akbar Ghazinour ,  Hao Li ,  Gilles Montoriol ,  Didier Salle ,  Pierre Savary

发明人： Christophe Landez ,  Hugues Beaulaton ,  Thierry Cassagnes ,  Stephane Colomines ,  Robert G. Gach ,  Akbar Ghazinour ,  Hao Li ,  Gilles Montoriol ,  Didier Salle ,  Pierre Savary

IPC分类号： G01S7/28

CPC分类号： G01S7/35 ,  G01S7/032 ,  G01S13/34 ,  G01S13/931 ,  G01S2013/9325 ,  H03C3/0925 ,  H03L7/1976

摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

摘要翻译： 集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。 频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑 并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

公开(公告)号：US09628093B2

公开(公告)日：2017-04-18

申请号：US14899499

申请日：2013-07-18

申请人： Birama Goumballa ,  Gilles Montoriol ,  Didier Salle

发明人： Birama Goumballa ,  Gilles Montoriol ,  Didier Salle

IPC分类号： H03L7/06 ,  H03L7/089 ,  H03K17/567 ,  H03L7/18

CPC分类号： H03L7/0896 ,  H03K17/567 ,  H03L7/18

摘要： A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

公开(公告)号：US09401723B2

公开(公告)日：2016-07-26

申请号：US14709686

申请日：2015-05-12

申请人： Gilles Montoriol ,  Olivier Vincent Doare ,  Birama Goumballa ,  Didier Salle

发明人： Gilles Montoriol ,  Olivier Vincent Doare ,  Birama Goumballa ,  Didier Salle

IPC分类号： H03L7/06 ,  H03L7/097 ,  H03L7/093 ,  H03L7/095

CPC分类号： H03L7/1976 ,  H03L7/085

摘要： An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.

摘要翻译： 用于锁相环PLL的XOR相位检测器包括具有用于周期性参考信号的输入的XOR门和连接到PLL的分频器的另一输入。 电平移位器具有连接到异或门的输出的电平移位器输入和可连接到PLL的压控振荡器VCO的电平移位器输出。 电平转换器可连接低电压供电器和高电平供电器之间，具有高电平和低电平。 电平移位器被设置为根据XOR相位检测器的输出端的电压是低还是高来在其输出端输出高电平或低电平。 电平移位器还具有用于将高电平设置为设定值电平的设定值输入。

公开(公告)号：US09720074B2

公开(公告)日：2017-08-01

申请号：US14324322

申请日：2014-07-07

申请人： Didier Salle ,  Olivier Doare ,  Christophe Landez

发明人： Didier Salle ,  Olivier Doare ,  Christophe Landez

IPC分类号： G01S7/40 ,  G01S13/02 ,  G01S7/03 ,  G01S13/34 ,  H03C3/09 ,  G01S13/58 ,  G01S13/93

CPC分类号： G01S7/4008 ,  G01S7/032 ,  G01S13/02 ,  G01S13/343 ,  G01S13/584 ,  G01S13/931 ,  H03C3/0925

摘要： A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.

公开(公告)号：US08731502B2

公开(公告)日：2014-05-20

申请号：US13145125

申请日：2010-02-10

申请人： Didier Salle ,  Olivier Doare ,  Stephane Dugalleix

发明人： Didier Salle ,  Olivier Doare ,  Stephane Dugalleix

IPC分类号： H04B1/18

CPC分类号： G01S7/35 ,  G01S7/032 ,  G01S13/34 ,  G01S13/931 ,  G01S2013/9325 ,  H03C3/0925 ,  H03L7/1976

摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for use in an automotive radar system. The frequency generation circuitry comprises low-path modulation circuitry arranged to generate a first, low-path control signal for providing lower frequency modulation of the frequency source, the low-path modulation circuitry comprising a Phase Locked Loop (PLL) arranged to generate the low-path control signal for controlling the frequency source and a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control module operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of at least a first, lower frequency pattern control signal. The frequency generation circuitry further comprises high-path modulation circuitry arranged to generate a second, high-path control signal for providing higher frequency modulation of the frequency source.

摘要翻译： 集成电路包括用于控制在汽车雷达系统中使用的频率源的频率产生电路。 频率产生电路包括低通道调制电路，其被布置为产生用于提供频率源的较低频率调制的第一低路径控制信号，该低通道调制电路包括被配置为产生低电平的锁相环（PLL） 用于控制频率源的PATH控制信号和位于PLL的反馈环路内的分数N分频器，以及频率模式控制模块，其可操作地耦合到分数N分频器，并被布置成通过以下方式控制分数N分频器 至少第一低频模式控制信号。 频率产生电路还包括被设置为产生用于提供频率源的更高频率调制的第二高路径控制信号的高路径调制电路。

公开(公告)号：US20090270057A1

公开(公告)日：2009-10-29

申请号：US12295738

申请日：2006-04-03

申请人： Didier Salle ,  Arnaud Girardot ,  Gerald Haennig ,  Pierre Savary

发明人： Didier Salle ,  Arnaud Girardot ,  Gerald Haennig ,  Pierre Savary

IPC分类号： H01Q11/12

CPC分类号： H03F3/24 ,  H03F1/0205 ,  H03F1/0261 ,  H03F1/302 ,  H03F1/303 ,  H03F2200/27 ,  H04B1/006 ,  H04B1/04 ,  H04B2001/0408

摘要： A wireless communication unit comprises a transmitter having a power amplifier biased by a bias circuit and a controller operably coupled to the bias circuit for setting one or more bias levels of the power amplifier. The bias circuit is a single bias circuit and is configured to provide either a current mode bias control of the power amplifier or a voltage mode bias control of the power amplifier in response to a control signal from the controller. In this manner, a single bias control circuit can be used to support applications that benefit from both current mode bias control and voltage mode bias control of the power amplifier.

摘要翻译： 无线通信单元包括具有由偏置电路偏置的功率放大器的发射器和可操作地耦合到偏置电路的控制器，用于设置功率放大器的一个或多个偏置电平。 偏置电路是单个偏置电路，并且被配置为响应于来自控制器的控制信号，提供功率放大器的电流模式偏置控制或功率放大器的电压模式偏置控制。 以这种方式，单个偏置控制电路可用于支持受益于功率放大器的电流模式偏置控制和电压模式偏置控制的应用。

公开(公告)号：US07605652B2

公开(公告)日：2009-10-20

申请号：US12063012

申请日：2005-08-05

申请人： Hugues Beaulaton ,  Gerald Haennig ,  Didier Salle

发明人： Hugues Beaulaton ,  Gerald Haennig ,  Didier Salle

IPC分类号： H03G3/20

CPC分类号： H03F1/02 ,  H03F1/0272 ,  H03F2200/105 ,  H03F2200/78

摘要： The output power of an RF power amplifier is controlled using a feedback loop including a differential integrator for controlling the amplifier's bias voltage. The gain of integration in the differential integrator is varied so as to compensate for variations in the derivative of the power amplifier output power versus the bias voltage.

摘要翻译： 使用包括用于控制放大器的偏置电压的差分积分器的反馈回路来控制RF功率放大器的输出功率。 差分积分器的积分增益是变化的，以便补偿功率放大器输出功率相对于偏置电压的导数的变化。

公开(公告)号：US06449020B1

公开(公告)日：2002-09-10

申请号：US09268971

申请日：1999-03-16

申请人： Didier Salle ,  Gérard Bret

发明人： Didier Salle ,  Gérard Bret

IPC分类号： H04N964

CPC分类号： H04N9/68

摘要： A device for regulating the amplitude of a chrominance signal includes a variable gain amplifier having an input receiving a sub-carrier signal, and an output providing a regulated sub-carrier signal. The gain of the amplifier is controlled by two regulation loops. The first regulation loop operates during the duration of the reference burst. The second regulation loop operates during the visible line. Each of these loops include an up/down counter controlled by a clock. A digital-analog converter has an input receiving the output signals from the first and second up/down counters. An output signal from the digital-analog converter is connected to the gain control of the amplifier. The digital-analog amplifier is controlled by another clock.

摘要翻译： 用于调节色度信号的幅度的装置包括具有接收副载波信号的输入的可变增益放大器和提供调节的副载波信号的输出。 放大器的增益由两个调节回路控制。 第一调节回路在参考脉冲串的持续时间内运行。 第二个调节回路在可见行期间运行。 这些循环中的每一个包括由时钟控制的上/下计数器。 数模转换器具有接收来自第一和第二上/下计数器的输出信号的输入。 来自数模转换器的输出信号连接到放大器的增益控制。 数字模拟放大器由另一个时钟控制。