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1.发明申请MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权包括集成电路存储器件的多字段寻址模式存储器系统公开(公告)号：US20140003131A1
公开(公告)日：2014-01-02
申请号：US13860825
申请日：2013-04-11
IPC分类号： G11C8/10
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。
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公开(公告)号：US08595459B2
公开(公告)日：2013-11-26
申请号：US10998402
申请日：2004-11-29
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0673 , G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
摘要翻译： 微线程存储器件。 提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为至少最小访问时间间隔必须在对存储单元的给定行的连续访问之间发生。 提供传送控制电路以响应于第一存储器访问请求在多个存储体和外部信号路径之间传送第一数据量，第一数据量小于外部信号路径带宽和 最小访问时间间隔。
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3.发明申请MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权包括集成电路存储器件的多字段寻址模式存储器系统公开(公告)号：US20120170399A1
公开(公告)日：2012-07-05
申请号：US13410254
申请日：2012-03-01
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。
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4.发明授权Multi-column addressing mode memory system including an integrated circuit memory device 有权多列寻址模式存储器系统，包括集成电路存储器件公开(公告)号：US08154947B2
公开(公告)日：2012-04-10
申请号：US13239846
申请日：2011-09-22
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。
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5.发明申请MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权包括集成电路存储器件的多字段寻址模式存储器系统公开(公告)号：US20090193202A1
公开(公告)日：2009-07-30
申请号：US12391873
申请日：2009-02-24
IPC分类号： G06F12/00
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。
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6.发明授权Multi-column addressing mode memory system including an integrated circuit memory device 有权多列寻址模式存储器系统，包括集成电路存储器件公开(公告)号：US08432766B2
公开(公告)日：2013-04-30
申请号：US13410254
申请日：2012-03-01
IPC分类号： G11C8/14
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。
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7.发明申请MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权包括集成电路存储器件的多字段寻址模式存储器系统公开(公告)号：US20120020178A1
公开(公告)日：2012-01-26
申请号：US13239846
申请日：2011-09-22
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。
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8.发明授权Multi-column addressing mode memory system including an integrated circuit memory device 有权多列寻址模式存储器系统，包括集成电路存储器件公开(公告)号：US07505356B2
公开(公告)日：2009-03-17
申请号：US11853708
申请日：2007-09-11
IPC分类号： G11C8/14
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。
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9.发明授权Multi-column addressing mode memory system including an integrated circuit memory device 有权多列寻址模式存储器系统，包括集成电路存储器件公开(公告)号：US08908466B2
公开(公告)日：2014-12-09
申请号：US13860825
申请日：2013-04-11
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。
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10.发明授权公开(公告)号：US08050134B2
公开(公告)日：2011-11-01
申请号：US13019785
申请日：2011-02-02
IPC分类号： G11C8/14
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
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