公开(公告)号：US09129666B1

公开(公告)日：2015-09-08

申请号：US13590495

申请日：2012-08-21

申请人： Wayne S. Richardson ,  Wayne Frederick Ellis ,  Yohan Usthavia Frans ,  Lawrence Lai

发明人： Wayne S. Richardson ,  Wayne Frederick Ellis ,  Yohan Usthavia Frans ,  Lawrence Lai

IPC分类号： G11C7/00 ,  G11C7/22

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C29/023 ,  G11C29/028

摘要： A memory device is placed in a mode that redefines the command set used to control the memory device. This may occur either in anticipation of the memory system falling out of calibration, or after it has already fallen out of calibration. The redefined command set is designed such that it may be reliably received by the memory device at the specified rate even if the memory system has fallen out of calibration. The redefined command set is then used to issue command(s) to recalibrate one or more communication links such that they can exchange data, commands, and/or addresses at a specified rate. After recalibration, the memory device is returned to responding to the original command set.

摘要翻译： 存储器件被放置在重新定义用于控制存储器件的命令集的模式中。 这可能发生在预期的存储器系统脱离校准，或者在它已经脱离校准之后。 重新定义的命令集被设计成即使存储器系统已经脱离校准，也可以以指定的速率被存储器件可靠地接收。 然后，重新定义的命令集用于发出命令以重新校准一个或多个通信链路，使得它们可以以指定的速率交换数据，命令和/或地址。 重新校准后，内存设备将返回以响应原始命令集。

公开(公告)号：US08942056B2

公开(公告)日：2015-01-27

申请号：US13980826

申请日：2012-02-15

申请人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

发明人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC分类号： G11C5/14 ,  G06F1/32 ,  G11C7/02 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C29/02

CPC分类号： G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

摘要翻译： 在一个实施例中，存储器设备包括存储器核心和用于接收命令和数据的输入接收器。 存储器装置还包括寄存器，用于存储指示输入接收器的子集是否响应于控制信号掉电的值。 存储器控制器将命令和数据发送到存储器件。 存储器控制器还发送该值以指示存储器件的输入接收器的子集是否响应于控制信号掉电。 此外，响应于自我新命令，存储装置延迟进入自刷新操作，直到接收到接收到自刷新命令后接收的控制信号为止。

公开(公告)号：US08908466B2

公开(公告)日：2014-12-09

申请号：US13860825

申请日：2013-04-11

申请人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

发明人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

IPC分类号： G11C8/14 ,  G11C8/16 ,  G11C8/12 ,  G11C8/10

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。

公开(公告)号：US08391099B2

公开(公告)日：2013-03-05

申请号：US13103548

申请日：2011-05-09

申请人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

发明人： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC分类号： G11C8/18

CPC分类号： G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

摘要翻译： 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US08271747B2

公开(公告)日：2012-09-18

申请号：US12493424

申请日：2009-06-29

申请人： Lawrence Lai

发明人： Lawrence Lai

IPC分类号： G06F12/00

CPC分类号： G06F13/4234 ,  Y02D10/14 ,  Y02D10/151

摘要： An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from the resulting set of candidates so a memory write operation consumes less power (relative to selection of other keys), or so that the operation minimizes switching noise. The selected mask key is then substituted by a controller into masked data values, and a modified data block is transmitted to memory, with the memory detecting masked data by identifying mask keys in the modified data block.

摘要翻译： 改进的数据系统允许功率效率的掩模密钥写入操作。 掩码密钥选择器实现基于对块数据的掩码密钥写入操作的掩码密钥的基于标准的选择。 在一个实施例中，将第一组掩码密钥与将被写入存储器的数据块的数据字节进行比较。 比较从与未屏蔽的数据字节匹配的候选列表中选择密钥，即将作为“已更改”数据写入内存的值。 从所得到的候选集中选择掩码密钥，因此存储器写入操作消耗较少的功率（相对于其他密钥的选择），或者使得操作使切换噪声最小化。 所选择的掩码密钥然后由控制器代替为被屏蔽的数据值，并且修改的数据块被发送到存储器，通过在修改的数据块中识别掩码密钥，存储器检测屏蔽数据。

公开(公告)号：US08050134B2

公开(公告)日：2011-11-01

申请号：US13019785

申请日：2011-02-02

申请人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

发明人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

IPC分类号： G11C8/14

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

公开(公告)号：US07907470B2

公开(公告)日：2011-03-15

申请号：US12391873

申请日：2009-02-24

申请人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

发明人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

IPC分类号： G11C8/14

CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。

公开(公告)号：US06114679A

公开(公告)日：2000-09-05

申请号：US155399

申请日：1998-09-29

申请人： Lawrence Lai ,  Neilson Zeng

发明人： Lawrence Lai ,  Neilson Zeng

IPC分类号： B65D81/34 ,  H05B6/80

CPC分类号： B65D81/3446 ,  B65D2581/3441 ,  B65D2581/3468 ,  B65D2581/3489 ,  B65D2581/3494 ,  Y10S99/14

摘要： A microwave energy heating element has a plurality of spaced microwave components generally arranged in a closed loop pattern. Each of the microwave components (42, 44) has a non-resonant length. When the heating element is in a loaded condition with a load juxtaposed thereto for capacitively coupling the microwave components together, the microwave components cooperatively redistribute impinging microwave energy. When the heating element is in an unloaded condition, the microwave components act independently remaining inert to impinging microwave energy.

摘要翻译： PCT No.PCT / CA98 / 00047 Sec。 371日期：1998年9月29日 102（e）1998年9月29日PCT PCT 1998年1月29日PCT公布。 第WO98 / 33724号公报 日期1998年8月6日微波能量加热元件具有通常以闭环图案布置的多个间隔开的微波部件。 每个微波组件（42,44）具有非共振长度。 当加热元件处于与其并置的负载的负载状态以将微波部件电容耦合在一起时，微波部件协同地重新分布冲击微波能量。 当加热元件处于无负载状态时，微波组件独立地起作用以保持惰性以撞击微波能量。

公开(公告)号：US5748554A

公开(公告)日：1998-05-05

申请号：US771303

申请日：1996-12-20

申请人： Richard M. Barth ,  Donald C. Stark ,  Lawrence Lai ,  Wayne S. Richardson

发明人： Richard M. Barth ,  Donald C. Stark ,  Lawrence Lai ,  Wayne S. Richardson

IPC分类号： G11C7/06 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4091 ,  B11C13/00

CPC分类号： G11C7/06 ,  G11C11/4085 ,  G11C11/4091 ,  G11C8/14

摘要： A memory and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group and is coupled to the memory cells in the row of the corresponding sub-group. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.

摘要翻译： 描述了存储器和操作方法。 在一个实施例中，存储器包括分成多个子组的一组存储器单元。 子字线选择性地耦合到主字线，每个子字线对应于子组，并且被耦合到相应子组的行中的存储器单元。 感测放大器电路耦合到该组存储器单元。 感测放大器电路被分成多个子感测电路，多个子感测电路中的每一个选择性地耦合到多个子组中对应的一个子组。 存储器包括一个控制机制，用于控制在任何一个时间被激活的字线和子感测电路，使得只需要执行存储器操作所需的那些子字线和子感测电路并消耗功率。 在替代实施例中，控制机构控制子字线和子感测电路以使得能够从存储器的不同行实质上并发地访问存储器单元的不同子组。

公开(公告)号：US08595459B2

公开(公告)日：2013-11-26

申请号：US10998402

申请日：2004-11-29

申请人： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

发明人： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G09G5/399

CPC分类号： G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

摘要翻译： 微线程存储器件。 提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为至少最小访问时间间隔必须在对存储单元的给定行的连续访问之间发生。 提供传送控制电路以响应于第一存储器访问请求在多个存储体和外部信号路径之间传送第一数据量，第一数据量小于外部信号路径带宽和 最小访问时间间隔。