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公开(公告)号：US20150332069A1
公开(公告)日：2015-11-19
申请号：US14809683
申请日：2015-07-27
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Joseph C. Circello , Daniel M. McCarthy , John D. Mitchell , Peter J. Wilson , John J. Vaglica
CPC classification number: G06F21/85 , G06F12/1458 , G06F21/74
Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
Abstract translation: 可以对可以被配置为在特定安全模式（例如具有一个或多个信道的直接存储器访问（DMA））中作为主机的设备的存储位置进行编程，以指示当被配置为 作为主设备运行。
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Patent Agency Ranking
公开(公告)号：US20140105101A1
公开(公告)日：2014-04-17
申请号：US13649461
申请日：2012-10-11
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Mieu Van Vu , John J. Vaglica
IPC: H04W88/08
CPC classification number: H04L1/0008 , H04W24/06 , Y02D70/00
Abstract: A method and apparatus automatically maintains a JESD204 serial data link (252) as active by using an idle signal (254) and multiplexer selection circuit (247) to selectively switch signal data samples (246) and dummy samples (0, . . . 0) onto a serial interface input to a JESD module (248) for serialization into a plurality of symbols for transmission over the JESD204 serial data link (252) in response to a transmit clock signal (253) so that serialized symbols generated from signal data samples are transmitted when there are signal data samples available, and serialized symbols generated from dummy samples are transmitted when there are no signal data samples available.
Abstract translation: 一种方法和装置通过使用空闲信号（254）和多路复用器选择电路（247）自动地将JESD204串行数据链路（252）维持有效，以选择性地切换信号数据样本（246）和虚拟样本（0，...） ）到输入到JESD模块（248）的串行接口，用于串行化成多个符号，以响应于发送时钟信号（253）在JESD204串行数据链路（252）上传输，从而从信号数据样本产生的串行化符号 当有信号数据样本可用时发送，并且当没有信号数据样本可用时，从伪样本生成的串行符号被发送。
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公开(公告)号：US08964791B2
公开(公告)日：2015-02-24
申请号：US13649461
申请日：2012-10-11
Applicant: Freescale Semiconductor, Inc.
Inventor： Mieu Van Vu , John J. Vaglica
CPC classification number: H04L1/0008 , H04W24/06 , Y02D70/00
Abstract: A method and apparatus automatically maintains a JESD204 serial data link (252) as active by using an idle signal (254) and multiplexer selection circuit (247) to selectively switch signal data samples (246) and dummy samples (0, . . . 0) onto a serial interface input to a JESD module (248) for serialization into a plurality of symbols for transmission over the JESD204 serial data link (252) in response to a transmit clock signal (253) so that serialized symbols generated from signal data samples are transmitted when there are signal data samples available, and serialized symbols generated from dummy samples are transmitted when there are no signal data samples available.
Abstract translation: 一种方法和装置通过使用空闲信号（254）和多路复用器选择电路（247）自动地将JESD204串行数据链路（252）维持有效，以选择性地切换信号数据样本（246）和虚拟样本（0，...） ）到输入到JESD模块（248）的串行接口，用于串行化成多个符号，以响应于发送时钟信号（253）在JESD204串行数据链路（252）上传输，从而从信号数据样本产生的串行化符号 当有信号数据样本可用时发送，并且当没有信号数据样本可用时，从伪样本生成的串行符号被发送。
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公开(公告)号：US09824242B2
公开(公告)日：2017-11-21
申请号：US14809683
申请日：2015-07-27
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Joseph C. Circello , Daniel M. McCarthy , John D. Mitchell , Peter J. Wilson , John J. Vaglica
CPC classification number: G06F21/85 , G06F12/1458 , G06F21/74
Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
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5.发明申请Method and System for Automatically Controlling the Insertion of Control Word in CPRI Daisy Chain Configuration 有权用于自动控制CPRI菊花链配置中控制字插入的方法和系统公开(公告)号：US20140094157A1
公开(公告)日：2014-04-03
申请号：US13632549
申请日：2012-10-01
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Tuongvu V. Nguyen , John J. Vaglica , Roy Shor , Somvir Dahiya , Ori Goren , Avraham Horn , Arvind Kaushik , Arindam Sinha , Puneet Wadhawan
IPC: H04W88/08
CPC classification number: H04W88/085
Abstract: A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link (561) by providing a hardware control mechanism (504-509) at a local radio base station subsystem (501) connected in a CPRI daisy chain configuration between a downstream RE device (570) and an upstream REC device (560) for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.
Abstract translation: 一种方法和装置通过在以CPRI菊花链配置连接的本地无线电基站子系统（501）处提供硬件控制机制（504-509）来自动控制通过共享CPRI链路（561）插入信息流数据， 下游RE设备（570）和上游REC设备（560），用于确定正在发送的控制字是源自下游设备（例如，来自下游RE设备的转发数据）还是来自本地设备。
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6.发明授权Method and system for automatically controlling the insertion of control word in CPRI daisy chain configuration 有权用于自动控制CPRI菊花链配置中控制字插入的方法和系统公开(公告)号：US09392640B2
公开(公告)日：2016-07-12
申请号：US13632549
申请日：2012-10-01
Applicant: Freescale Semiconductor, Inc.
Inventor： Tuongvu V. Nguyen , John J. Vaglica , Roy Shor , Somvir Dahiya , Ori Goren , Avraham Horn , Arvind Kaushik , Arindam Sinha , Puneet Wadhawan
CPC classification number: H04W88/085
Abstract: A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link (561) by providing a hardware control mechanism (504-509) at a local radio base station subsystem (501) connected in a CPRI daisy chain configuration between a downstream RE device (570) and an upstream REC device (560) for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.
Abstract translation: 一种方法和装置通过在以CPRI菊花链配置连接的本地无线电基站子系统（501）处提供硬件控制机制（504-509）来自动控制通过共享CPRI链路（561）插入信息流数据， 下游RE设备（570）和上游REC设备（560），用于确定正在发送的控制字是源自下游设备（例如，来自下游RE设备的转发数据）还是来自本地设备。
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