公开(公告)号：US09424176B2

公开(公告)日：2016-08-23

申请号：US13776052

申请日：2013-02-25

Applicant: Freescale Semiconductor, Inc.

Inventor： Ross S. Scouller ,  Jeffrey C. Cunningham ,  Horacio P. Gasquet

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7209

Abstract: A brownout tolerant EEPROM emulator (18) manages memory operations at a volatile memory (20) and non-volatile memory (24) using a plurality of sector status bits (451) and forward/reverse skip flags (452, 453) stored in a sector identification record (45) of each sector to define a plurality of status indicators arranged sequentially to specify a plurality of sector configuration states for each memory sector, and to automatically bypass one or more dead sectors in the non-volatile memory array during forward copydown and reverse search operations.

Abstract translation: 使用多个扇区状态位（451）和存储在存储器中的正向/反向跳过标志（452,453）来管理易失性存储器（20）和非易失性存储器（24）中的存储器操作， 每个扇区的扇区识别记录（45），以定义顺序地布置的多个状态指示符，以指定每个存储器扇区的多个扇区配置状态，并且在正向协作期间自动绕过非易失性存储器阵列中的一个或多个死扇区 和反向搜索操作。

公开(公告)号：US09690571B2

公开(公告)日：2017-06-27

申请号：US14144891

申请日：2013-12-31

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Ross S. Scouller ,  Jeffrey C. Cunningham ,  Christopher N. Hume

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/00 ,  G06F13/28 ,  G06F9/445 ,  G06F3/06 ,  G06F9/32 ,  G06F9/24

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/0617 ,  G06F3/0679 ,  G06F8/654 ,  G06F9/24 ,  G06F9/328

Abstract: A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching is provided for just a small area of the possible flash memory map, and program flow is controlled by presenting the CPU core's own address to redirect the program counter to the patch area.

公开(公告)号：US10157093B2

公开(公告)日：2018-12-18

申请号：US14722632

申请日：2015-05-27

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jeffrey C. Cunningham ,  Ross S. Scouller

IPC: G06F11/07 ,  G11C16/34 ,  G11C29/50 ,  G11C29/52 ,  G06F11/10 ,  G11C7/00 ,  G11C7/20 ,  G11C29/42 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56 ,  G11C29/44

Abstract: A memory system includes a memory array, control circuitry, and comparator circuitry. The memory array includes a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution. The first plurality and second plurality of programmed bitcells are programmed with a same set of data values. The control circuitry is configured to provide a read request to the memory array and receive read data in response to the read request, wherein the read data comprises first read data from the first section and second read data from the second section. The comparator circuitry is configured to compare the first read data to the second read data and generate an error indicator in response to the compare.

公开(公告)号：US09792191B2

公开(公告)日：2017-10-17

申请号：US14829877

申请日：2015-08-19

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Ross S. Scouller ,  Melody B. Caron ,  Jeffrey C. Cunningham

IPC: G06F11/00 ,  G06F11/20 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F11/2069 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/2087 ,  G06F12/0246 ,  G06F2201/805 ,  G06F2212/1032 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7209

Abstract: A method of operating an emulated electrically erasable (EEE) memory system includes entering a quick write mode for a predetermined amount of time, upon detection of imminent power loss of the EEE memory system. A first write request is received immediately subsequent to entering the quick write mode, where the first write request includes a first address of an emulated memory of the EEE memory system and associated first data to be written at the first address. A first new record is created in non-volatile memory of the EEE memory system during the quick write mode, where the first new record includes the first address, the associated first data, and a blank record status identifier. The first new record is updated to have a quick record status ID, in response to a determination that record data of the first new record passes verification.

公开(公告)号：US20140244895A1

公开(公告)日：2014-08-28

申请号：US13776052

申请日：2013-02-25

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Ross S. Scouller ,  Jeffrey C. Cunningham ,  Horacio P. Gasquet

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7209

Abstract: A brownout tolerant EEPROM emulator (18) manages memory operations at a volatile memory (20) and non-volatile memory (24) using a plurality of sector status bits (451) and forward/reverse skip flags (452, 453) stored in a sector identification record (45) of each sector to define a plurality of status indicators arranged sequentially to specify a plurality of sector configuration states for each memory sector, and to automatically bypass one or more dead sectors in the non-volatile memory array during forward copydown and reverse search operations.

Abstract translation: 使用多个扇区状态位（451）和存储在存储器中的正向/反向跳过标志（452,453）来管理易失性存储器（20）和非易失性存储器（24）中的存储器操作， 每个扇区的扇区识别记录（45），以定义顺序地布置的多个状态指示符，以指定每个存储器扇区的多个扇区配置状态，并且在正向协作期间自动绕过非易失性存储器阵列中的一个或多个死扇区 和反向搜索操作。