公开(公告)号：US5075761A

公开(公告)日：1991-12-24

申请号：US567270

申请日：1990-08-14

申请人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

发明人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

IPC分类号： H01L21/285 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/76895 ,  H01L23/53271 ,  H01L2924/0002

摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.

摘要翻译： 在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。 然后将该结构图案化以在有效区域上形成栅极区域。 在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。 通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护第一金属硅化物层免受损坏。

公开(公告)号：US06617242B1

公开(公告)日：2003-09-09

申请号：US08480543

申请日：1995-06-07

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

IPC分类号： H01L2144

CPC分类号： H01L21/76858 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

摘要翻译： 在半导体集成电路中制造层间接触的方法提供通过绝缘层形成接触开口。 一层难熔金属或难熔金属合金沉积在集成电路芯片的表面上。 然后在显着提高的温度下沉积铝层，使得在铝层和难熔金属层之间的界面处形成铝/难熔金属合金。 这种合金的形成导致接触开口内的金属膨胀，从而填充接触开口并为沉积的铝层提供光滑的上部轮廓。

公开(公告)号：US06242811B1

公开(公告)日：2001-06-05

申请号：US09080066

申请日：1998-05-15

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/28512 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

摘要翻译： 通过形成通过绝缘层的接触开口来制造半导体集成电路中的层间接触。 一层难熔金属或难熔金属合金沉积在集成电路芯片的表面上。 然后在显着提高的温度下沉积铝层，使得在铝层和难熔金属层之间的界面处形成铝/难熔金属合金。 这种合金的形成导致接触开口内的金属膨胀，从而填充接触开口并为沉积的铝层提供光滑的上部轮廓。

公开(公告)号：USRE35111E

公开(公告)日：1995-12-05

申请号：US984084

申请日：1992-11-30

申请人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

发明人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/76895 ,  H01L23/53271 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/02

摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the rust metal silicide layer from damage.

摘要翻译： 在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。 然后将该结构图案化以在有效区域上形成栅极区域。 在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。 通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护防锈金属硅化物层免受损坏。

公开(公告)号：US5930673A

公开(公告)日：1999-07-27

申请号：US418122

申请日：1995-04-06

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Yih-Shung Lin ,  Girish A. Dixit ,  Che-Chia Wei

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Yih-Shung Lin ,  Girish A. Dixit ,  Che-Chia Wei

IPC分类号： H01L21/28 ,  C23C16/02 ,  C23C16/20 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/283

CPC分类号： H01L21/76843 ,  C23C16/0281 ,  C23C16/20 ,  H01L21/28512 ,  H01L21/32051 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

摘要翻译： 提供了一种用于在半导体集成电路器件中沉积铝薄膜层以形成接触的方法。 所有或一些沉积过程在允许改善沉积的铝原子的表面迁移的温度下以相对较低的沉积速率进行。 在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。 低温沉积步骤可以通过沉积铝来开始，而包含集成电路器件的晶片正在从沉积室内的较冷的温度加热。

公开(公告)号：US5108951A

公开(公告)日：1992-04-28

申请号：US609883

申请日：1990-11-05

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Yih-Shung Lin ,  Girish A. Dixit ,  Che-Chia Wei

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Yih-Shung Lin ,  Girish A. Dixit ,  Che-Chia Wei

IPC分类号： H01L21/28 ,  C23C16/02 ,  C23C16/20 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L21/76843 ,  C23C16/0281 ,  C23C16/20 ,  H01L21/28512 ,  H01L21/32051 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

公开(公告)号：US4978637A

公开(公告)日：1990-12-18

申请号：US359860

申请日：1989-05-31

申请人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

发明人： Fu-Tai Liou ,  Yih-Shung Lin ,  Fusen E. Chen

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/76895 ,  H01L23/53271 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/02

摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.

摘要翻译： 在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。 然后将该结构图案化以在有效区域上形成栅极区域。 在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。 通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护第一金属硅化物层免受损坏。

公开(公告)号：US06433435B1

公开(公告)日：2002-08-13

申请号：US09086884

申请日：1998-05-29

申请人： Yih-Shung Lin ,  Fu-Tai Liou

发明人： Yih-Shung Lin ,  Fu-Tai Liou

IPC分类号： H01L2348

摘要： A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

公开(公告)号：US5841195A

公开(公告)日：1998-11-24

申请号：US448703

申请日：1995-05-24

申请人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John Leonard Walters

发明人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John Leonard Walters

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L2924/0002

摘要： A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

摘要翻译： 提供了一种用于在集成电路中形成接触通孔的方法。 首先，在集成电路中的绝缘层上形成第一缓冲层。 第一缓冲层具有与绝缘层不同的蚀刻速率。 然后在第一缓冲层上形成第二缓冲层，其中第二缓冲层具有比第一缓冲层快的蚀刻速率。 执行各向同性蚀刻以产生通过第二缓冲层和第一缓冲层的一部分的开口。 因为第二缓冲层比第一缓冲层蚀刻更快，所以可以控制开口的侧壁的倾斜。 然后进行各向异性蚀刻以完成接触通孔的形成。

公开(公告)号：US5246883A

公开(公告)日：1993-09-21

申请号：US832088

申请日：1992-02-06

申请人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John L. Walters

发明人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John L. Walters

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L2924/0002

摘要： A method is provided for forming contact vias in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.