公开(公告)号：US06878245B2

公开(公告)日：2005-04-12

申请号：US10085338

申请日：2002-02-27

Applicant: Srinivas Gandikota ,  Chris R. McGuirk ,  Deenesh Padhi ,  Sivakami Ramanathan ,  Muhammad Atif Malik ,  Girish A. Dixit

Inventor： Srinivas Gandikota ,  Chris R. McGuirk ,  Deenesh Padhi ,  Sivakami Ramanathan ,  Muhammad Atif Malik ,  Girish A. Dixit

IPC: C25D21/14 ,  C25D21/18 ,  C25D17/00 ,  C25D21/00

CPC classification number: C25D21/18 ,  C25D21/14

Abstract: Embodiments of the invention generally provide an apparatus and method for replenishing organic molecules in an electroplating bath. The replenishment process of the present invention may occur on a real-time basis, and therefore, the concentration of organics minimally varies from desired concentration levels. The replenishment method generally includes conducting pre-processing depletion measurements in order to determine organic depletion rates per current density applied in the electroplating system. Once the organic depletion rates per current density are determined, these depletion rates may be applied to an electroplating processing recipe to calculate the volume of organic depletion per recipe step. The calculated volume of organic depletion per recipe step may then be used to determine the volume of organic molecule replenishment per unit of time that is required per recipe step in order to maintain a desired concentration of organics in the plating solution. The calculated replenishment volume may then be added to the processing recipe so that the replenishment process may occur at real-time during processing periods. The apparatus generally includes a selectively actuated valve in communicaiton with a fluid delivery line, wherein the valve is configured to fluidly isolate a plating cell during a non-processing time period. The valve may be controlled by a system controller, and thus, the fluid level in the cell may be controlled during a non-processing time period.

Abstract translation: 本发明的实施方案通常提供用于在电镀浴中补充有机分子的装置和方法。 本发明的补充方法可以在实时的基础上进行，因此有机物的浓度最小化从期望的浓度水平变化。 补充方法通常包括进行预处理耗尽测量，以便确定在电镀系统中施加的每个电流密度的有机耗尽率。 一旦确定了每个电流密度的有机耗尽率，则这些耗尽率可以应用于电镀处理配方以计算每个配方步骤的有机耗尽量。 然后可以使用每个配方步骤的计算的有机耗尽体积来确定每个配方步骤所需的每单位时间的有机分子补充体积，以维持电镀溶液中所需的有机物浓度。 计算的补充量然后可以被添加到处理配方中，使得补货过程可以在处理时段期间实时发生。 该装置通常包括与流体输送管线通信的选择性致动的阀，其中阀被配置为在非处理时间段期间流体地隔离电镀槽。 阀可以由系统控制器控制，因此，可以在非处理时间段期间控制单元中的液位。

公开(公告)号：US06358849B1

公开(公告)日：2002-03-19

申请号：US09467680

申请日：1999-12-21

Applicant: Robert H. Havemann ,  Girish A. Dixit ,  Manoj Jain ,  Eden Zielinski ,  Qi-Zhong Hong ,  Jeffrey West

Inventor： Robert H. Havemann ,  Girish A. Dixit ,  Manoj Jain ,  Eden Zielinski ,  Qi-Zhong Hong ,  Jeffrey West

IPC: H01L21302

CPC classification number: H01L21/76808 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867

Abstract: A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

Abstract translation: 一种双嵌入互连制造方法，在沟槽蚀刻中沟槽蚀刻和去除填充物之后，在通孔中使用临时填料。 这在沟槽蚀刻期间通过底部保护提供。

公开(公告)号：US06333265B1

公开(公告)日：2001-12-25

申请号：US08766199

申请日：1996-12-12

Applicant: Girish A. Dixit ,  Anthony Konecni ,  Robert H. Havemann

Inventor： Girish A. Dixit ,  Anthony Konecni ,  Robert H. Havemann

IPC: H01L2144

CPC classification number: H01L21/76882 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76862

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;

Abstract translation: 提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。 这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即， 〜3.0）。 优选地，空腔设置有不含钛的衬垫以促进空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地 在约100°-300℃的温度下不超过约30Mpa。以上述方式填充的空腔表现出比通过常规实践填充的结构小至多30％的电阻水平。

公开(公告)号：US06268297B1

公开(公告)日：2001-07-31

申请号：US09196725

申请日：1998-11-20

Applicant: Somnath S. Nag ,  Gregory B. Shinn ,  Girish A. Dixit

Inventor： Somnath S. Nag ,  Gregory B. Shinn ,  Girish A. Dixit

IPC: H01L21469

CPC classification number: H01L21/02304 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31604 ,  H01L21/31625 ,  H01L21/76801

Abstract: A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.

Abstract translation: 在高密度等离子体化学气相沉积技术中使用基于膦的化学的低温预金属介电沉积方法。 该方法使用在低于350℃下沉积的高达3.5％（重量）的磷掺杂氧化物，能够在没有微孔的多晶硅栅极之间填充0.4微米的空间。

公开(公告)号：US06159847A

公开(公告)日：2000-12-12

申请号：US191027

申请日：1998-11-12

Applicant: Robert H. Havemann ,  Girish A. Dixit

Inventor： Robert H. Havemann ,  Girish A. Dixit

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/7685 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: AlCu alloys with higher Cu content are added in thin layers within a metallization structure. The increased Cu content provided by the thin layer improves interconnect reliability and reduces the effects of electromigration with minimal effect on plasma etch and cleanup processes.

Abstract translation: 具有较高Cu含量的AlCu合金以金属化结构内的薄层加入。 由薄层提供的增加的Cu含量提高了互连可靠性，并且减少电迁移的影响，对等离子体蚀刻和清除过程的影响最小。

公开(公告)号：US5849367A

公开(公告)日：1998-12-15

申请号：US764674

申请日：1996-12-11

Applicant: Girish A. Dixit ,  Anthony J. Konecni

Inventor： Girish A. Dixit ,  Anthony J. Konecni

IPC: C23C14/02 ,  H01L21/768

CPC classification number: H01L21/76846 ,  C23C14/022 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76877

Abstract: An elemental titanium-free liner and cavity cleansing process is provided that allows for the elimination of conventional sputter etch and elemental titanium depositions. A low power plasma etch provides for pre-conditioning/cleansing of cavities such as contacts and vias. A refractory metal is provided as a cavity liner. Preferably, the liner is comprised of several discrete refractory metal liner layers, each having a thickness of about 25-100 .ANG., that can be applied by CVD and/or PVD. A low power plasma cleanse is preferably interposed between each liner layer deposition. A suitable metal plug can be deposited and directed into the cavity to complete cavity filling. Preferably, the metal plug is an elemental aluminum or aluminum alloy plug that is deposited by CVD and force-filled into the cavity to reduce the incidence of micro-voids within the cavity. Elimination of the conventional sputter etch and the high temperature processing (temp..gtoreq..sup..about. 400.degree. C.) associated with such processing allows for the use of polymeric dielectrics, such as the family of polytetrafluorethylene ("PTFE") compounds, which exhibit a dielectric constant (.kappa.) of about 1.9; parylene (.kappa.=.sup..about. 2.2-2.6); aerogels and xerogels (.kappa.=.sup..about. 1.1-1.8); and the family of polymeric spin-on-glass ("SOG") materials; use of all the foregoing materials being attractive because of the ability of these materials to reduce parasitic capacitance of the interconnects. Because these polymeric materials are temperature sensitive, their use has been limited, as conventional device fabrication practices typically require operation temperatures far in excess of the melting and/or decomposition temperature for these materials.

Abstract translation: 提供了元素无钛衬里和空腔清洁工艺，其允许消除常规的溅射蚀刻和元素钛沉积。 低功率等离子体蚀刻提供诸如触点和通孔之类的空腔的预调节/清洁。 提供难熔金属作为空腔衬垫。 优选地，衬套由几个分立的难熔金属衬垫层组成，每层具有约25-100的厚度，可以通过CVD和/或PVD施加。 优选地，在每个衬垫层沉积之间插入低功率等离子体清洁。 可以将合适的金属塞子沉积并引导到空腔中以完成空腔填充。 优选地，金属插塞是元素铝或铝合金插塞，其通过CVD沉积并强力填充到空腔中以减少空腔内的微孔的入射。 消除常规的溅射蚀刻和与这种处理相关的高温处理（温度> = = DIFFERENCE 400℃）允许使用聚合物电介质，例如聚四氟乙烯（“PTFE”）族化合物，其表现出 介电常数（kappa）约为1.9; 聚对二甲苯（kappa = DIFFERENCE 2.2-2.6）; 气凝胶和干凝胶（kappa = DIFFERENCE 1.1-1.8）; 和聚合物旋涂玻璃（“SOG”）材料的家族; 使用所有上述材料是有吸引力的，因为这些材料能够减少互连的寄生电容。 由于这些聚合物材料是温度敏感的，因此其使用受到限制，因为传统的器件制造实践通常需要远远超过这些材料的熔化和/或分解温度的操作温度。

公开(公告)号：US5847457A

公开(公告)日：1998-12-08

申请号：US738040

申请日：1996-10-24

Applicant: Fusen E. Chen ,  Fu-Tai Liou ,  Girish A. Dixit

Inventor： Fusen E. Chen ,  Fu-Tai Liou ,  Girish A. Dixit

IPC: H01L23/522 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L2924/0002

Abstract: A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.

Abstract translation: 提供一种用于形成半导体集成电路的接触开口或通路的方法，以及根据该集成电路形成的集成电路。 在下面的区域上形成第一金属区域。 在集成电路上形成第一绝缘层。 然后在第一绝缘层上形成第二绝缘层。 蚀刻第二绝缘层的一部分以暴露第一绝缘层的一部分，其中暴露的第一绝缘层和剩余的第二绝缘层形成基本平坦的表面。 在暴露的第一绝缘层和剩余的第二绝缘层上形成金属氧化物层。 在金属氧化物层上形成并图案化光致抗蚀剂层。 然后选择性地蚀刻金属氧化物层以形成露出第一绝缘层的一部分的通孔。 然后选择性地蚀刻通孔中的第一绝缘层以暴露第一金属区域的一部分。 去除光致抗蚀剂层，然后在金属氧化物层上形成第二金属层，并在通孔中与第一金属区接触。

公开(公告)号：US5593921A

公开(公告)日：1997-01-14

申请号：US438167

申请日：1995-05-09

Applicant: Fusen E. Chen ,  Fu-Tai Liou ,  Girish A. Dixit

Inventor： Fusen E. Chen ,  Fu-Tai Liou ,  Girish A. Dixit

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/441

CPC classification number: H01L21/76802 ,  Y10S148/043 ,  Y10S148/118

Abstract: A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.

Abstract translation: 提供一种用于形成半导体集成电路的接触开口或通路的方法，以及根据该集成电路形成的集成电路。 在下面的区域上形成第一金属区域。 在集成电路上形成第一绝缘层。 然后在第一绝缘层上形成第二绝缘层。 蚀刻第二绝缘层的一部分以暴露第一绝缘层的一部分，其中暴露的第一绝缘层和剩余的第二绝缘层形成基本平坦的表面。 在暴露的第一绝缘层和剩余的第二绝缘层上形成金属氧化物层。 在金属氧化物层上形成并图案化光致抗蚀剂层。 然后选择性地蚀刻金属氧化物层以形成露出第一绝缘层的一部分的通孔。 然后选择性地蚀刻通孔中的第一绝缘层以暴露第一金属区域的一部分。 去除光致抗蚀剂层，然后在金属氧化物层上形成第二金属层，并在通孔中与第一金属区接触。

公开(公告)号：US5521411A

公开(公告)日：1996-05-28

申请号：US271565

申请日：1994-07-07

Applicant: Fusen E. Chen ,  Frank R. Bryant ,  Girish A. Dixit

Inventor： Fusen E. Chen ,  Frank R. Bryant ,  Girish A. Dixit

IPC: H01L21/266 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L29/6656

Abstract: A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. the oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.

Abstract translation: 提供一种用于形成集成电路的晶体管间隔物蚀刻端点结构的方法，以及根据该集成电路形成的集成电路。 栅极形成在衬底的一部分上。 在集成电路上形成电介质层，并且在电介质层上形成氧化物层。 对氧化物层进行图案化和蚀刻以在栅极的每一侧和电介质层的一部分上形成侧壁氧化物间隔物。 然后除去未被侧壁氧化物间隔物覆盖的电介质层。

公开(公告)号：US5348901A

公开(公告)日：1994-09-20

申请号：US911167

申请日：1992-07-09

Applicant: Fusen E. Chen ,  Girish A. Dixit ,  Robert O. Miller

Inventor： Fusen E. Chen ,  Girish A. Dixit ,  Robert O. Miller

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L27/00 ,  H01L27/10 ,  H01L27/11 ,  H01L21/205 ,  H01L21/285

CPC classification number: H01L28/20 ,  H01L21/76889 ,  H01L27/1112

Abstract: A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.

Abstract translation: 提供一种用于形成半导体集成电路的多晶硅电阻性负载元件的方法和根据该集成电路形成的集成电路。 具有第一类型的导电性的轻掺杂的第一导电层。 在集成电路上形成第一氧化物层，其中第一开口穿过其暴露第一导电层的一部分。 使用第一氧化物层作为掩模，然后用第二导电类型的掺杂剂注入第一导电层的暴露部分，以形成暴露部分和被掩模覆盖的部分之间的结。 然后在第一开口中的第一氧化物层的一部分上形成第二氧化物区域，并且在接合处以及暴露的第一导电层的与接合部相邻的部分上形成第二氧化物区域。 在第一导电层的暴露部分上形成硅化物。