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    Semiconductor integrated circuit device and a method of manufacturing the same
    2.
    发明授权
    Semiconductor integrated circuit device and a method of manufacturing the same 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US06762444B2

    公开(公告)日：2004-07-13

    申请号：US10308001

    申请日：2002-12-03

    申请人： Fumio Ootsuka ,  Yusuke Nonaka ,  Satoshi Shimamoto ,  Sohei Omori ,  Hideto Kazama

    发明人： Fumio Ootsuka ,  Yusuke Nonaka ,  Satoshi Shimamoto ,  Sohei Omori ,  Hideto Kazama

    IPC分类号： H01L21336

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： In order to improve the performance of a semiconductor integrated circuit device wherein a capacitor provided between storage nodes of an SRAM and a device having an analog capacitor are formed on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are further formed over the local wiring LIc. According to the same process step as the local wiring, capacitive insulating film and upper electrode formed in the memory cell forming area, a local wiring LIc, a capacitive insulating film and an upper electrode are formed over a silicon oxide film in an analog capacitor forming area and a plug in the silicon oxide film.

    摘要翻译： 为了提高半导体集成电路器件的性能，其中在单个衬底上形成在SRAM的存储节点和具有模拟电容器的器件之间提供的电容器，在一对n上的氧化硅膜中形成插头 存储单元形成区域中的沟道型MISFET以及用于连接该n沟道型MISFET的各个栅电极和漏极的局部布线LIc形成在氧化硅膜和插塞上。 此后，在本地布线LIc上进一步形成电容绝缘膜和上电极。 根据与形成在存储单元形成区域中的局部布线，电容绝缘膜和上电极，局部布线LIc，电容绝缘膜和上电极相同的处理步骤，形成在模拟电容器形成中的氧化硅膜上 区域并插入氧化硅膜。

    Semiconductor integrated circuit device
    3.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06635937B2

    公开(公告)日：2003-10-21

    申请号：US10152615

    申请日：2002-05-23

    申请人： Fumio Ootsuka ,  Yusuke Nonaka ,  Satoshi Shimamoto ,  Sohei Omori ,  Hideto Kazama

    发明人： Fumio Ootsuka ,  Yusuke Nonaka ,  Satoshi Shimamoto ,  Sohei Omori ,  Hideto Kazama

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： To improve performance, a capacitor is provided between storage nodes of an SRAM and a device having an analog capacitor on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are formed over the local wiring LIc.

    摘要翻译： 为了提高性能，在SRAM的存储节点和在单个基板上具有模拟电容器的器件之间提供电容器，在存储单元形成区域中的一对n沟道型MISFET上的氧化硅膜中形成插头， 并且在氧化硅膜和插塞之上形成用于连接一对n沟道型MISFET的各个栅电极和漏极的局部布线LIc。 此后，在局部布线LIc上形成电容绝缘膜和上电极。

    Regeneration method and apparatus of wafer and substrate
    4.
    发明授权
    Regeneration method and apparatus of wafer and substrate 失效
    晶圆和基片再生方法及装置

    公开(公告)号：US5981301A

    公开(公告)日：1999-11-09

    申请号：US804732

    申请日：1997-02-21

    申请人： Kazuo Muramatsu ,  Akihiro Kawai ,  Tsutomu Watanabe ,  Satoshi Shimamoto

    发明人： Kazuo Muramatsu ,  Akihiro Kawai ,  Tsutomu Watanabe ,  Satoshi Shimamoto

    IPC分类号： B24B51/00 ,  B24B53/00 ,  H01L21/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/66 ,  H01L23/544 ,  H01L21/00

    CPC分类号： H01L22/34 ,  B24B37/042 ,  H01L21/02032 ,  H01L2924/0002 ,  Y10S438/906 ,  Y10S438/959

    摘要： A method for regenerating a used wafer or substrate by removing a functional coating film formed on the used wafer or substrate, comprising the steps of:(a) a step for sorting the used wafer or substrate according to the quality, structure or thickness of the functional coating film;(b) a step for removing the functional coating film, while in a state of holding the used wafer or substrate, (i) by lapping the objective face of the used wafer or substrate with a hard metal-bonded whetstone while applying an electrochemical in-process dressing, (ii) by polishing the objective face while dropping a fine-particle polishing slurry between a polishing plate provided with a pad and the functional coating film, or (iii) by electrolyzing the functional coating film on the objective face placed opposite to an electrode face in an electrolyte solution at a predetermined voltage;(c) a step for mechanically removing the functional coating film adhered to the end face at an adequate stage; and(d) a step for washing and drying the used wafer or substrate after removal of the functional coating film.

    摘要翻译： 一种用于通过去除在所使用的晶片或衬底上形成的功能性涂层来再生所使用的晶片或衬底的方法，包括以下步骤：（a）根据质量，结构或厚度对所使用的晶片或衬底进行分选的步骤 功能性涂膜; （b）在保持所使用的晶片或基板的状态下，（i）通过用硬质金属结合的砂轮研磨所使用的晶片或基板的物镜，同时施加电化学 （ii）通过抛光目标面，同时在设置有衬垫的抛光板和功能性涂膜之间滴下细粒抛光浆料，或（iii）通过电解相对放置的物镜面上的功能性涂膜 以预定电压在电解质溶液中的电极面; （c）在足够的阶段机械去除附着在端面上的功能性涂膜的步骤; 以及（d）除去功能性涂膜后，对使用过的晶片或基板进行清洗干燥的工序。

    Semiconductor device and manufacturing method thereof
    7.
    发明申请
    Semiconductor device and manufacturing method thereof 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20050269640A1

    公开(公告)日：2005-12-08

    申请号：US11143716

    申请日：2005-06-03

    申请人： Satoshi Shimamoto ,  Katsuhiko Ichinose

    发明人： Satoshi Shimamoto ,  Katsuhiko Ichinose

    IPC分类号： H01L27/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A technique for forming a plurality of MISFETs having desired threshold voltages on a SOI substrate is provided. Each gate electrodes of pMIS and nMIS is made of a metal film having a work function approximate to that of a channel region of the pMIS, such as a molybdenum or ruthenium film, and a rise of the threshold voltage due to the metal film is reduced by inducing a positive fixed charge in a BOX layer. Thereby, the pMIS and nMIS having the desired threshold voltages can be formed on the SOI substrate.

    摘要翻译： 提供了一种用于在SOI衬底上形成具有期望阈值电压的多个MISFET的技术。 pMIS和nMIS的每个栅电极由具有近似于pMIS的沟道区的功函数的函数函数（例如钼或钌膜）的金属膜制成，并且由于金属膜引起的阈值电压的上升减小 通过在BOX层中引起正固定电荷。 由此，可以在SOI衬底上形成具有所需阈值电压的pMIS和nMIS。