公开(公告)号：US20070138536A1

公开(公告)日：2007-06-21

申请号：US11609614

申请日：2006-12-12

申请人： Fumitaka ARAI ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Riichiro Shirota ,  Hiroshi Watanabe ,  Takamitsu Ishihara

发明人： Fumitaka ARAI ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Riichiro Shirota ,  Hiroshi Watanabe ,  Takamitsu Ishihara

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.

摘要翻译： NAND单元单元在第一导电类型的半导体层上形成有先进的栅极形成工艺，该第一导电类型的半导体层形成在第一导电类型的半导体衬底上，绝缘膜插入其间。 第一导电类型的第一杂质掺杂层形成在用作选择栅晶体管的沟道区的半导体层上。第一导电类型的位线接触和源极接触用第二杂质掺杂层形成在 位线和源极线接触部分，其侧壁被绝缘膜覆盖。

公开(公告)号：US07393748B2

公开(公告)日：2008-07-01

申请号：US11609614

申请日：2006-12-12

申请人： Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Riichiro Shirota ,  Hiroshi Watanabe ,  Takamitsu Ishihara

发明人： Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Riichiro Shirota ,  Hiroshi Watanabe ,  Takamitsu Ishihara

IPC分类号： H01L21/33

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.

摘要翻译： NAND单元单元在第一导电类型的半导体层上形成有先进的栅极形成工艺，该第一导电类型的半导体层形成在第一导电类型的半导体衬底上，绝缘膜插入其间。 第一导电类型的第一杂质掺杂层形成在用作选择栅晶体管的沟道区的半导体层上。第一导电类型的位线接触和源极接触用第二杂质掺杂层形成在 位线和源极线接触部分，其侧壁被绝缘膜覆盖。

公开(公告)号：US07459748B2

公开(公告)日：2008-12-02

申请号：US11549770

申请日：2006-10-16

申请人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

摘要翻译： 半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

公开(公告)号：US07539055B2

公开(公告)日：2009-05-26

申请号：US11763204

申请日：2007-06-14

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

摘要翻译： 非易失性半导体存储器包括多个存储单元晶体管，多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

公开(公告)号：US07528447B2

公开(公告)日：2009-05-05

申请号：US11396507

申请日：2006-04-05

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

摘要翻译： 一种包括多个存储单元晶体管的非易失性半导体存储器，所述多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

公开(公告)号：US20070237002A1

公开(公告)日：2007-10-11

申请号：US11763204

申请日：2007-06-14

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

IPC分类号： G11C16/24

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

摘要翻译： 非易失性半导体存储器包括多个存储单元晶体管，多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

公开(公告)号：US20060237706A1

公开(公告)日：2006-10-26

申请号：US11396507

申请日：2006-04-05

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Fumitaka Arai ,  Riichiro Shirota

IPC分类号： H01L47/00

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain-region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

摘要翻译： 一种包括多个存储单元晶体管的非易失性半导体存储器，所述多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

公开(公告)号：US07755134B2

公开(公告)日：2010-07-13

申请号：US11765881

申请日：2007-06-20

申请人： Masaru Kito ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

发明人： Masaru Kito ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

IPC分类号： H01L27/115

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

摘要翻译： 非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

公开(公告)号：US20070290253A1

公开(公告)日：2007-12-20

申请号：US11765881

申请日：2007-06-20

申请人： Masaru KITO ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

发明人： Masaru KITO ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

摘要翻译： 非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

公开(公告)号：US06980942B2

公开(公告)日：2005-12-27

申请号：US09812365

申请日：2001-03-20

申请人： Naoki Kusunoki ,  Nobutoshi Aoki ,  Hirotaka Amakawa

发明人： Naoki Kusunoki ,  Nobutoshi Aoki ,  Hirotaka Amakawa

IPC分类号： G06F17/10 ,  G06F17/50 ,  H01L21/00

CPC分类号： G06F17/5018

摘要： Plural boundary points are generated on a string on the surface of a material and a first length of a line segment between the boundary points is obtained. Then, the displacement of the boundary point according to a process model and the boundary point is moved by the displacement. A second length of the line segment between the boundary points after the boundary point is moved is found. When the second length is greater than a value obtained by multiplying the first length by a first factor exceeding 1, a new boundary point is added to the line segment whereas when the second length is smaller than a value obtained by multiplying the first length by a second factor less than 1, one of the boundary points of the line segment is eliminated.

摘要翻译： 在材料的表面上的弦上产生多个边界点，并且获得边界点之间的线段的第一长度。 然后，根据过程模型和边界点的边界点的位移由位移移动。 发现边界点移动后边界点之间的线段的第二长度。 当第二长度大于通过将第一长度乘以第一因子超过1而获得的值时，新的边界点被添加到线段，而当第二长度小于通过将第一长度乘以一个 第二个因子小于1，线段的边界点之一被消除。