公开(公告)号：US07459748B2

公开(公告)日：2008-12-02

申请号：US11549770

申请日：2006-10-16

申请人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

摘要翻译： 半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

公开(公告)号：US20070102749A1

公开(公告)日：2007-05-10

申请号：US11549770

申请日：2006-10-16

申请人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunokii ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunokii ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

摘要翻译： 半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

公开(公告)号：US07602013B2

公开(公告)日：2009-10-13

申请号：US11649752

申请日：2007-01-05

申请人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Kouji Matsuo

发明人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Kouji Matsuo

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/66621

摘要： A semiconductor device includes: a layer provided on or above a semiconductor substrate, having an opening, and containing Si and Ge; and a gate provided at a position corresponding to the opening. It is possible to provide a semiconductor device and a manufacturing method of the same which realize easy control of a recess amount and reduction in damage at the time of the recessing.

摘要翻译： 半导体器件包括：设置在半导体衬底上或上方的具有开口并且包含Si和Ge的层; 以及设置在与开口相对应的位置处的门。 可以提供一种半导体器件及其制造方法，其实现容易控制凹陷量并减少凹陷时的损伤。

公开(公告)号：US20080224252A1

公开(公告)日：2008-09-18

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

摘要翻译： 在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸， 以防止形成小平面。 随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

公开(公告)号：US20060076624A1

公开(公告)日：2006-04-13

申请号：US11282784

申请日：2005-11-18

申请人： Hajime Nagano ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Hajime Nagano ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/76251 ,  H01L21/84

摘要： A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.

摘要翻译： 公开了一种半导体衬底，其包括第一单晶硅层，形成为部分地覆盖第一单晶硅层的一个主表面的绝缘体，形成为覆盖第一单晶硅层的区域的第二单晶硅层， 不覆盖绝缘体，并且覆盖邻近该区域的绝缘体的边缘部分，以及形成在绝缘体上的非单晶硅层，非单晶硅层与第二单晶硅之间的界面 层位于绝缘体上。

公开(公告)号：US06989316B2

公开(公告)日：2006-01-24

申请号：US10406281

申请日：2003-04-04

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L21/20

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

公开(公告)号：US06617226B1

公开(公告)日：2003-09-09

申请号：US09609107

申请日：2000-06-30

申请人： Kyoioni Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoioni Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L2120

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

摘要翻译： 在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸， 以防止形成小平面。 随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

公开(公告)号：US20050035413A1

公开(公告)日：2005-02-17

申请号：US10947161

申请日：2004-09-23

申请人： Kiyotaka Miyano ,  Kazuya Ohuchi ,  Ichiro Mizushima

发明人： Kiyotaka Miyano ,  Kazuya Ohuchi ,  Ichiro Mizushima

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336 ,  H01L29/76 ,  H01L31/113

CPC分类号： H01L29/66628

摘要： A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.

摘要翻译： 半导体器件包括：半导体衬底; 形成在所述半导体衬底的顶表面上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 在半导体衬底中形成的扩散层用作源极层和漏极层; 以及形成为覆盖所述扩散层的硅化物层; 其中氧浓度最大的氧浓度峰在垂直于所述顶表面的平面截取的横截面中处于比所述顶表面低的水平。

公开(公告)号：US20050006637A1

公开(公告)日：2005-01-13

申请号：US10743006

申请日：2003-12-23

申请人： Toshihiko Iinuma ,  Ichiro Mizushima ,  Mitsuaki Izuha ,  Kiyotaka Miyano ,  Kyoichi Suguro

发明人： Toshihiko Iinuma ,  Ichiro Mizushima ,  Mitsuaki Izuha ,  Kiyotaka Miyano ,  Kyoichi Suguro

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/66477 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

摘要： There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.

公开(公告)号：US06570217B1

公开(公告)日：2003-05-27

申请号：US09296669

申请日：1999-04-22

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

IPC分类号： H01L2926

CPC分类号： H01L29/66583 ,  H01L21/324 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7831 ,  H01L29/78639

摘要： To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.