利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.03 秒)

    Nonvolatile semiconductor storage device having conductive and insulative charge storage films
    3.
    发明授权
    Nonvolatile semiconductor storage device having conductive and insulative charge storage films 有权
    具有导电和绝缘电荷存储膜的非易失性半导体存储装置

    公开(公告)号：US08710572B2

    公开(公告)日：2014-04-29

    申请号：US12339993

    申请日：2008-12-19

    申请人： Takamitsu Ishihara ,  Koichi Muraoka

    发明人： Takamitsu Ishihara ,  Koichi Muraoka

    IPC分类号： H01L29/423

    CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/7881 ,  H01L29/792

    摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.

    摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储装置，包括：半导体衬底; 源极区和漏极区，形成在所述半导体衬底中以便彼此分离并且在其间限定沟道区; 形成在沟道区上的隧道绝缘膜; 形成在隧道绝缘膜上的绝缘电荷存储膜; 形成在绝缘性电荷存储膜上的导电性电荷存储膜比沟道方向上的绝缘性电荷存储膜短; 形成在导电性电荷存储膜上的层间绝缘膜; 以及形成在层间绝缘膜上的栅电极。

    Semiconductor memory device and method of manufacturing the same
    4.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US07420241B2

    公开(公告)日：2008-09-02

    申请号：US11283622

    申请日：2005-11-21

    申请人： Takamitsu Ishihara

    发明人： Takamitsu Ishihara

    IPC分类号： H01L29/788

    CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521

    摘要： A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode and the source layer.

    摘要翻译： 半导体存储器件包括：存储单元，其包括设置在半导体衬底上的第一栅极绝缘膜; 设置在所述第一栅极绝缘膜上的浮栅; 设置在所述浮栅电极上的第二栅极绝缘膜; 设置在所述第二栅极绝缘膜上的控制栅电极; 设置在所述半导体衬底中的源极层和漏极层，所述源极层和所述漏极层分别设置在所述浮动栅电极下方的沟道区域的任一侧; 源电极，其电连接到所述源极层; 设置在漏极层上的缓冲膜; 以及存储单元，其包括通过缓冲膜电连接到漏极层的漏电极，其中当从上方观察半导体衬底的表面时，浮置栅电极和漏极层之间的重叠区域小于 浮栅电极和源层。

    Semiconductor memory device and method of manufacturing the same
    5.
    发明申请
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20060267067A1

    公开(公告)日：2006-11-30

    申请号：US11283622

    申请日：2005-11-21

    申请人： Takamitsu Ishihara

    发明人： Takamitsu Ishihara

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521

    摘要： A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode and the source layer.

    摘要翻译： 半导体存储器件包括：存储单元，其包括设置在半导体衬底上的第一栅极绝缘膜; 设置在所述第一栅极绝缘膜上的浮栅; 设置在所述浮栅电极上的第二栅极绝缘膜; 设置在所述第二栅极绝缘膜上的控制栅电极; 设置在所述半导体衬底中的源极层和漏极层，所述源极层和所述漏极层分别设置在所述浮动栅电极下方的沟道区域的任一侧; 源电极，其电连接到所述源极层; 设置在漏极层上的缓冲膜; 以及存储单元，其包括通过缓冲膜电连接到漏极层的漏电极，其中当从上方观察半导体衬底的表面时，浮置栅电极和漏极层之间的重叠区域小于 浮栅电极和源层。

    Nonvolatile semiconductor memory device and manufacturing method thereof
    6.
    发明授权
    Nonvolatile semiconductor memory device and manufacturing method thereof 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US07821057B2

    公开(公告)日：2010-10-26

    申请号：US12457757

    申请日：2009-06-19

    申请人： Takamitsu Ishihara

    发明人： Takamitsu Ishihara

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source and drain diffusion regions. An edge of the stacked structure in the vicinity of the source region is formed away from a junction position between the source diffusion region and the channel region.

    摘要翻译： 非易失性半导体存储器件包括第一导电类型的半导体衬底，在半导体衬底的表面上相对形成的第二导电类型的一对源极和漏极扩散区域，以及具有栅极绝缘膜，电荷 累积膜，层间绝缘膜和控制栅极，其顺序地形成在介于源极扩散区域和漏极扩散区域之间的半导体衬底的表面的沟道区域上。 在源极区附近的层叠结构的边缘远离源极扩散区域和沟道区域之间的接合位置。

    Nonvolatile semiconductor memory device and manufacturing method thereof
    7.
    发明申请
    Nonvolatile semiconductor memory device and manufacturing method thereof 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20080001203A1

    公开(公告)日：2008-01-03

    申请号：US11643904

    申请日：2006-12-22

    申请人： Takamitsu Ishihara

    发明人： Takamitsu Ishihara

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source and drain diffusion regions. An edge of the stacked structure in the vicinity of the source region is formed away from a junction position between the source diffusion region and the channel region.

    摘要翻译： 非易失性半导体存储器件包括第一导电类型的半导体衬底，在半导体衬底的表面上相对形成的第二导电类型的一对源极和漏极扩散区域，以及具有栅极绝缘膜，电荷 累积膜，层间绝缘膜和控制栅极，其顺序地形成在介于源极扩散区域和漏极扩散区域之间的半导体衬底的表面的沟道区域上。 在源极区附近的层叠结构的边缘远离源极扩散区域和沟道区域之间的接合位置。

    Semiconductor device
    8.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20050051856A1

    公开(公告)日：2005-03-10

    申请号：US10882275

    申请日：2004-07-02

    申请人： Mizuki Ono ,  Takamitsu Ishihara

    发明人： Mizuki Ono ,  Takamitsu Ishihara

    IPC分类号： H01L21/316 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94

    CPC分类号： H01L29/4983 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    摘要： The semiconductor device includes a gate insulator with a three-layer stacked structure including a first insulator on a semiconductor substrate, a second insulator on the first insulator, and a third insulator on the second insulator. The first insulator is made of silicon oxide, silicon nitride, or oxinitrided silicon. The second and the third insulator contain a metal. The dielectric constant of the second insulator is higher than the square root of the product of the dielectric constants of the first and the third insulator. The present invention provides a high-speed semiconductor device, decreasing scattering of the carriers.

    摘要翻译： 半导体器件包括具有三层堆叠结构的栅极绝缘体，其包括在半导体衬底上的第一绝缘体，第一绝缘体上的第二绝缘体和第二绝缘体上的第三绝缘体。 第一绝缘体由氧化硅，氮化硅或氧化氮化硅制成。 第二和第三绝缘体含有金属。 第二绝缘体的介电常数高于第一和第三绝缘体的介电常数乘积的平方根。 本发明提供了一种降低载流子散射的高速半导体器件。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20080286924A1

    公开(公告)日：2008-11-20

    申请号：US12180904

    申请日：2008-07-28

    申请人： Takamitsu Ishihara

    发明人： Takamitsu Ishihara

    IPC分类号： H01L21/336

    CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521

    摘要： A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode and the source layer.

    摘要翻译： 半导体存储器件包括：存储单元，其包括设置在半导体衬底上的第一栅极绝缘膜; 设置在第一栅极绝缘膜上的浮栅电极; 设置在所述浮栅电极上的第二栅极绝缘膜; 设置在所述第二栅极绝缘膜上的控制栅电极; 设置在所述半导体衬底中的源极层和漏极层，所述源极层和所述漏极层分别设置在所述浮动栅电极下方的沟道区域的任一侧; 源电极，其电连接到所述源极层; 设置在漏极层上的缓冲膜; 以及存储单元，其包括通过缓冲膜电连接到漏极层的漏电极，其中当从上方观察半导体衬底的表面时，浮置栅电极和漏极层之间的重叠区域小于 浮栅电极和源层。

    Complementary field effect transistor and its manufacturing method
    10.
    发明授权
    Complementary field effect transistor and its manufacturing method 有权
    互补场效应晶体管及其制造方法

    公开(公告)号：US07087969B2

    公开(公告)日：2006-08-08

    申请号：US10760501

    申请日：2004-01-21

    申请人： Akira Nishiyama ,  Mizuki Ono ,  Masato Koyama ,  Takamitsu Ishihara

    发明人： Akira Nishiyama ,  Mizuki Ono ,  Masato Koyama ,  Takamitsu Ishihara

    IPC分类号： H01L29/76 ,  H01L31/119

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/518

    摘要： A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode. The p-type field effect transistor has: a second gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and including substantially no positive charge; a second gate electrode provided on the second gate insulating film; and p-type source and drain regions provided on both sides of the second gate electrode.

    摘要翻译： 互补场效应晶体管包括：半导体衬底; 设置在半导体衬底上的n型场效应晶体管; 以及设置在半导体基板上的p型场效应晶体管。 n型场效应晶体管具有：包含含有选自IV族金属和镧系金属的元素的氧化物的第一栅极绝缘膜，并且还含有元素和III族元素的化合物; 设置在所述第一栅极绝缘膜上的第一栅电极; 以及形成在第一栅电极的两侧上的n型源区和漏区。 p型场效应晶体管具有：第二栅极绝缘膜，其含有包含选自第Ⅳ族金属和镧系金属的元素的氧化物，并且基本上不含正电荷; 设置在所述第二栅极绝缘膜上的第二栅电极; 以及设置在第二栅电极的两侧的p型源区和漏区。