公开(公告)号：US20080151629A1

公开(公告)日：2008-06-26

申请号：US12020393

申请日：2008-01-25

申请人： Fumitoshi ITO ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi ITO ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C11/40 ,  H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US20100202205A1

公开(公告)日：2010-08-12

申请号：US12764090

申请日：2010-04-20

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US08576634B2

公开(公告)日：2013-11-05

申请号：US12764090

申请日：2010-04-20

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C11/34 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US07349250B2

公开(公告)日：2008-03-25

申请号：US11181721

申请日：2005-07-15

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C11/34

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US20060077713A1

公开(公告)日：2006-04-13

申请号：US11181721

申请日：2005-07-15

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US07719052B2

公开(公告)日：2010-05-18

申请号：US12020393

申请日：2008-01-25

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US07087955B2

公开(公告)日：2006-08-08

申请号：US10811830

申请日：2004-03-30

申请人： Yoshiyuki Kawashima ,  Fumitoshi Ito ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama

发明人： Yoshiyuki Kawashima ,  Fumitoshi Ito ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66833

摘要： A semiconductor device has a nonvolatile memory employing a split-gate type memory cell structure, using a nitride film as a charge storage layer. An n-type semiconductor region is formed in a main surface of a semiconductor substrate, and then, a memory gate electrode of a memory cell of a split gate type and a charge storage layer are formed over the semiconductor region. Subsequently, side walls are formed on side surfaces of the memory gate electrode, and a photoresist pattern is formed over the main surface of the semiconductor substrate. The photoresist pattern serves as an etching mask, and a part of the main surface of the semiconductor substrate is removed by etching to form a dent. In the region of the dent, the n-type semiconductor region is removed. Then, a p-type semiconductor region for forming a channel of an nMIS transistor for selecting a memory cell is formed.

摘要翻译： 半导体器件具有使用氮化物膜作为电荷存储层的采用分离栅型存储单元结构的非易失性存储器。 在半导体衬底的主表面中形成n型半导体区域，然后在半导体区域上形成分裂栅型存储单元的存储栅电极和电荷存储层。 随后，在存储栅电极的侧表面上形成侧壁，并且在半导体衬底的主表面上形成光刻胶图形。 光致抗蚀剂图案用作蚀刻掩模，并且通过蚀刻去除半导体衬底的主表面的一部分以形成凹陷。 在凹陷的区域中，去除n型半导体区域。 然后，形成用于形成用于选择存储单元的nMIS晶体管的沟道的p型半导体区域。

公开(公告)号：US07371631B2

公开(公告)日：2008-05-13

申请号：US11168639

申请日：2005-06-29

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US08390048B2

公开(公告)日：2013-03-05

申请号：US12904923

申请日：2010-10-14

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/00

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US07663176B2

公开(公告)日：2010-02-16

申请号：US12114074

申请日：2008-05-02

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/00

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。