公开(公告)号：US20100144108A1

公开(公告)日：2010-06-10

申请号：US12706668

申请日：2010-02-16

申请人： Takeshi SAKAI ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi SAKAI ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/8246

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US07371631B2

公开(公告)日：2008-05-13

申请号：US11168639

申请日：2005-06-29

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US08390048B2

公开(公告)日：2013-03-05

申请号：US12904923

申请日：2010-10-14

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/00

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US07663176B2

公开(公告)日：2010-02-16

申请号：US12114074

申请日：2008-05-02

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/00

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US20080206975A1

公开(公告)日：2008-08-28

申请号：US12114064

申请日：2008-05-02

申请人： Takeshi SAKAI ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi SAKAI ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/28

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US07863135B2

公开(公告)日：2011-01-04

申请号：US12706668

申请日：2010-02-16

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/00

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US20080203466A1

公开(公告)日：2008-08-28

申请号：US12114074

申请日：2008-05-02

申请人： Takeshi SAKAI ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi SAKAI ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

公开(公告)号：US20060003508A1

公开(公告)日：2006-01-05

申请号：US11168639

申请日：2005-06-29

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并且位于控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US07245531B2

公开(公告)日：2007-07-17

申请号：US11198191

申请日：2005-08-08

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。

公开(公告)号：US20060028868A1

公开(公告)日：2006-02-09

申请号：US11198191

申请日：2005-08-08

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34 ,  G11C5/06

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。