公开(公告)号：US20140239503A1

公开(公告)日：2014-08-28

申请号：US13778558

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括形成电连接到器件的金属接触结构。 在金属接触结构上选择性地形成覆盖层，并且在覆盖层上沉积层间绝缘材料。 金属硬掩模被沉积并在层间电介质材料上图案化以限定层间电介质材料的暴露区域。 该方法蚀刻层间电介质材料的暴露区域以露出覆盖层的至少一部分。 该方法包括用蚀刻剂去除金属硬掩模，同时封盖层将金属接触结构与蚀刻剂物理分离。 沉积金属以形成通过封盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US09305878B2

公开(公告)日：2016-04-05

申请号：US14570617

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L23/522 ,  H01L23/485 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括金属接触结构，形成在金属接触结构上的导电覆盖层，以及通过导电覆盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US20150097291A1

公开(公告)日：2015-04-09

申请号：US14570617

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括金属接触结构，形成在金属接触结构上的导电覆盖层，以及通过导电覆盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US08932911B2

公开(公告)日：2015-01-13

申请号：US13778558

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L21/4763 ,  H01L21/82 ,  H01L21/311 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括形成电连接到器件的金属接触结构。 在金属接触结构上选择性地形成覆盖层，并且在覆盖层上沉积层间绝缘材料。 金属硬掩模被沉积并在层间电介质材料上图案化以限定层间电介质材料的暴露区域。 该方法蚀刻层间电介质材料的暴露区域以露出覆盖层的至少一部分。 该方法包括用蚀刻剂去除金属硬掩模，同时封盖层将金属接触结构与蚀刻剂物理分离。 沉积金属以形成通过封盖层电连接到金属接触结构的导电通孔。