公开(公告)号：US08962421B2

公开(公告)日：2015-02-24

申请号：US13678011

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gopal Srinivasan ,  Andy Wei ,  Dinesh Somasekhar ,  Ali Keshavarzi ,  Subi Kengeri

IPC: H01L21/8234 ,  H01L21/20 ,  H01L49/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238

CPC classification number: H01L28/20 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78648

Abstract: A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.

Abstract translation: 一种制造FinFET集成电路的方法包括在扩散区的第二端处沉积第一多晶硅层，在扩散区的第二端沉积第二多晶硅层; 将n型材料扩散到扩散区域中以形成扩散电阻器; 并且在所述第一和第二多晶硅层之间外延生长硅材料，以在所述扩散电阻器上方形成翅片结构并跨越所述第一和第二多晶硅层。

公开(公告)号：US20140273474A1

公开(公告)日：2014-09-18

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Youngtag WOO ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。

公开(公告)号：US09105510B2

公开(公告)日：2015-08-11

申请号：US14461745

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Jongwook Kye ,  Dinesh Somasekhar

IPC: H01L21/8234 ,  H01L27/11 ,  H01L21/308 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/1108 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/11

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract translation: 公开了能够产生具有可变翅片间距小于40nm的翅片的方法，并且所得到的装置被公开。 实施例包括：在基板上形成硬掩模; 在硬掩模上提供第一和第二心轴; 在每个第一和第二心轴的每一侧上提供第一间隔件; 去除第一和第二心轴; 在移除所述第一和第二心轴之后，在每个所述第一间隔件的每一侧上提供第二间隔件; 并移除第一间隔物。

公开(公告)号：US08962483B2

公开(公告)日：2015-02-24

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/3065 ,  H01L21/308 ,  G03F7/26

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。

公开(公告)号：US20140134822A1

公开(公告)日：2014-05-15

申请号：US13678011

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Gopal Srinivasan ,  Andy Wei ,  Dinesh Somasekhar ,  Ali Keshavarzi ,  Subi Kengeri

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78648

Abstract: A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.

Abstract translation: 一种制造FinFET集成电路的方法包括在扩散区的第二端处沉积第一多晶硅层，在扩散区的第二端沉积第二多晶硅层; 将n型材料扩散到扩散区域中以形成扩散电阻器; 并且在所述第一和第二多晶硅层之间外延生长硅材料，以在所述扩散电阻器上方形成翅片结构并跨越所述第一和第二多晶硅层。