公开(公告)号：US20200227404A1

公开(公告)日：2020-07-16

申请号：US16244169

申请日：2019-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Jiehui Shu ,  Ruilong Xie ,  Yurong Wen ,  Garo J. Derderian ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L23/522

Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

公开(公告)号：US20140353728A1

公开(公告)日：2014-12-04

申请号：US13903694

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Garo J. Derderian

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/485 ,  H01L21/76805 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of capacitance reduction in a middle-of-the-line (MOL) nitride stack and a resulting device are disclosed. Embodiments include forming an oxide layer between one or more semiconductor devices on a wafer, the one or more semiconductor devices having source/drain junctions therebetween, forming a nitride layer over the one or more semiconductor devices and the oxide layer, forming a sacrificial oxide layer over the nitride layer, forming trenches through the oxide layer, the nitride layer, and the sacrificial oxide layer down to the source/drain junctions, forming a silicide in the trenches and on an upper surface of the sacrificial oxide layer, planarizing the silicide down to a point in the sacrificial oxide layer, and removing remaining sacrificial oxide to expose the nitride layer and a portion of the silicide protruding from an upper surface of the nitride layer.

Abstract translation: 公开了一种中间线（MOL）氮化物堆叠和所得到的器件中的电容减小的方法。 实施例包括在晶片上的一个或多个半导体器件之间形成氧化物层，所述一个或多个半导体器件之间具有源极/漏极结，在一个或多个半导体器件和氧化物层上形成氮化物层，形成牺牲氧化物层 在氮化物层上方，形成通过氧化物层，氮化物层和牺牲氧化物层的沟槽，直到源极/漏极结，在沟槽中和在牺牲氧化物层的上表面上形成硅化物，将硅化物平坦化 去除牺牲氧化物层中的一点，并且去除剩余的牺牲氧化物以暴露氮化物层和从氮化物层的上表面突出的硅化物的一部分。

公开(公告)号：US10510749B1

公开(公告)日：2019-12-17

申请号：US16057881

申请日：2018-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos ,  Garo J. Derderian

IPC: H01L29/76 ,  H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06

Abstract: A resistor for an integrated circuit (IC), an IC and a related method are disclosed. The resistor may include a metal alloy resistor body positioned within a single diffusion break (SDB). The SDB provides an isolation region in a semiconductor fin between a pair of fin-type field effect transistors (finFETs). The resistor in the SDB allows for the resistor to be built at front-end-of-line (FEOL) layers, which saves on space and expense, and allows for precise dimensions for the resistor.

公开(公告)号：US10276374B2

公开(公告)日：2019-04-30

申请号：US15709730

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Garo J. Derderian ,  Jinping Liu

IPC: H01L21/12 ,  H01L21/033 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/12

Abstract: The disclosure is directed to methods for forming a set of fins from a substrate. One embodiment of the disclosure includes: providing a stack over the substrate, the stack including a first oxide over the substrate, a first nitride over the pad oxide, a second oxide over the first nitride, and a first hardmask over the second oxide; patterning the first hard mask to form a first set of hardmask fins over the second oxide; oxidizing the first set of hardmask fins to convert the first set of hardmask fins into a set of oxide fins; using the set of oxide fins as a mask, etching the second oxide and the first nitride to expose portions of the first oxide thereunder such that remaining portions of the second oxide and the first nitride remain disposed beneath the set of oxide fins thereby defining a set of mask stacks; and using the set of mask stacks as a mask, etching the exposed portions of the first oxide and the substrate thereby forming the set of fins from the substrate.

公开(公告)号：US20190088478A1

公开(公告)日：2019-03-21

申请号：US15709730

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Garo J. Derderian ,  Jinping Liu

IPC: H01L21/033 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66

Abstract: The disclosure is directed to methods for forming a set of fins from a substrate. One embodiment of the disclosure includes: providing a stack over the substrate, the stack including a first oxide over the substrate, a first nitride over the pad oxide, a second oxide over the first nitride, and a first hardmask over the second oxide; patterning the first hard mask to form a first set of hardmask fins over the second oxide; oxidizing the first set of hardmask fins to convert the first set of hardmask fins into a set of oxide fins; using the set of oxide fins as a mask, etching the second oxide and the first nitride to expose portions of the first oxide thereunder such that remaining portions of the second oxide and the first nitride remain disposed beneath the set of oxide fins thereby defining a set of mask stacks; and using the set of mask stacks as a mask, etching the exposed portions of the first oxide and the substrate thereby forming the set of fins from the substrate.