公开(公告)号：US20180323191A1

公开(公告)日：2018-11-08

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： HAITING WANG ,  WEI ZHAO ,  HONG YU ,  XUSHENG WU ,  HUI ZANG ,  ZHENYU HU

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US20200373410A1

公开(公告)日：2020-11-26

申请号：US16423035

申请日：2019-05-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： TUNG-HSING LEE ,  SIPENG GU ,  JIEHUI SHU ,  HAITING WANG ,  ALI RAZAVIEH ,  WENJUN LI ,  KAVYA SREE DUGGIMPUDI ,  TAMILMANI ETHIRAJAN ,  BRADLEY MORGENFELD ,  DAVID NOEL POWER

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/45 ,  H01L21/311 ,  H01L21/285 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device is provided, which includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch and a plurality of second gate structures having a second gate pitch traversing across a first and a second set of fins, respectively. The second gate pitch is wider than the first gate pitch. Epitaxial regions are formed between adjacent second gate structures in the second set of fins. A dielectric layer is deposited over the second gate structures and the epitaxial regions. Contact openings are formed in the dielectric layer. At least one of the contact openings is formed over the second gate structure where the second gate structure traverses across the second set of fins. The contact openings are filled with a conductive material to form contact structures electrically coupled to the second gate structures.