公开(公告)号：US20180233566A1

公开(公告)日：2018-08-16

申请号：US15956090

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： SIPENG GU ,  XUSHENG WU ,  WENHE LIN ,  JEFFREY CHEE

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L21/321

CPC classification number: H01L21/26513 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.

公开(公告)号：US20180204920A1

公开(公告)日：2018-07-19

申请号：US15410159

申请日：2017-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： SIPENG GU ,  XUSHENG WU ,  WENHE LIN ,  JEFFREY CHEE

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/321 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/41783 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.

公开(公告)号：US20180240703A1

公开(公告)日：2018-08-23

申请号：US15438828

申请日：2017-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： SIPENG GU ,  XUSHENG WU ,  XINYUAN DOU ,  XIAOBO CHEN ,  GUOLIANG ZHU ,  WENHE LIN ,  JEFFREY CHEE

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L23/53266 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485

Abstract: Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.

公开(公告)号：US20180323191A1

公开(公告)日：2018-11-08

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： HAITING WANG ,  WEI ZHAO ,  HONG YU ,  XUSHENG WU ,  HUI ZANG ,  ZHENYU HU

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US20150333062A1

公开(公告)日：2015-11-19

申请号：US14809216

申请日：2015-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： XUSHENG WU ,  Wanxun He ,  Hongliang Shen

IPC: H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

Abstract translation: 本发明的实施例提供了一种用于制造鳍式场效应晶体管（finFET）的改进方法。 牺牲区域形成在半导体衬底上。 间隔件邻近牺牲区域的两侧形成。 翅片基于间隔件形成。 将一组间隔物作为假间隔物处理，并且在翅片形成之前被除去，留下用于在最终半导体结构上形成翅片的另一组间隔件。 最终半导体结构上的所有鳍都由牺牲材料的一侧上的间隔物形成。 这减少了散热片的宽度变化。