公开(公告)号：US20200343142A1

公开(公告)日：2020-10-29

申请号：US16396775

申请日：2019-04-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： JIEHUI SHU ,  RINUS TEK PO LEE ,  WEI HONG ,  HUI ZANG ,  HONG YU

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/285

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages. The present disclosure further provides a method of forming structures in a semiconductor device by forming a first and second cavities having sidewalls and bottom surfaces in a dielectric structure, where the first cavity has a narrower opening than the second cavity, forming a first material layer in the first and second cavities, forming a protective layer over the first material layer, where the protective layer fills the first cavity and conformally covers the sidewall and the bottom surfaces of the second cavity, performing a first isotropic etch on the protective layer to selectively remove a portion of the protective layer and form a retained portion of the protective layer, performing a second isotropic etch on the first material layer to selectively remove a portion of the first material layer and form a retained portion of the first material layer, removing the retained portion of the protective layer, and forming a second material layer in the first and second cavities, the second material layer being formed on the retained portion of the first material layer.

公开(公告)号：US20160086952A1

公开(公告)日：2016-03-24

申请号：US14961566

申请日：2015-12-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： HONG YU ,  HYUCKSOO YANG ,  RICHARD J. CARTER

IPC: H01L27/092 ,  H01L29/167 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/66795

Abstract: Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing. The oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash). The oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process.

公开(公告)号：US20180323191A1

公开(公告)日：2018-11-08

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： HAITING WANG ,  WEI ZHAO ,  HONG YU ,  XUSHENG WU ,  HUI ZANG ,  ZHENYU HU

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US20160211373A1

公开(公告)日：2016-07-21

申请号：US15080369

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： HONG YU ,  Hyucksoo Yang ,  Huang Liu ,  Richard J. Carter

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/24 ,  H01L29/267 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/8238 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.