公开(公告)号：US20180323191A1

公开(公告)日：2018-11-08

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： HAITING WANG ,  WEI ZHAO ,  HONG YU ,  XUSHENG WU ,  HUI ZANG ,  ZHENYU HU

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.