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    METHODS OF FORMING 3-D INTEGRATED SEMICONDUCTOR DEVICES HAVING INTERMEDIATE HEAT SPREADING CAPABILITIES
    1.
    发明申请
    METHODS OF FORMING 3-D INTEGRATED SEMICONDUCTOR DEVICES HAVING INTERMEDIATE HEAT SPREADING CAPABILITIES 有权
    形成具有中间热传递能力的3-D集成半导体器件的方法

    公开(公告)号：US20160190104A1

    公开(公告)日：2016-06-30

    申请号：US15064755

    申请日：2016-03-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

    IPC: H01L25/065 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: In a method of forming a three-dimensional semiconductor device, a first chip is provided that includes a first substrate, a first device layer positioned on and covering the first substrate, and a first metallization system positioned on and covering the first device layer, wherein the first device layer includes a plurality of first transistor elements. A second chip is also provided and includes a second substrate, a second device layer positioned on and covering the second substrate, and a second metallization system positioned on and covering the second device layer, wherein the second device layer includes a plurality of second transistor elements. The second chip is attached to the first chip so that a heat spreading material is positioned between the first chip and the second chip and covers at least a portion of the first metallization system.

    Abstract translation: 在形成三维半导体器件的方法中，提供了第一芯片，其包括第一衬底，位于第一衬底上并覆盖第一衬底的第一器件层，以及位于第一器件层上并覆盖第一器件层的第一金属化系统，其中 第一器件层包括多个第一晶体管元件。 还提供了第二芯片，并且包括第二衬底，位于第二衬底上并覆盖第二衬底的第二器件层，以及位于第二器件层上并覆盖第二器件层的第二金属化系统，其中第二器件层包括多个第二晶体管元件 。 第二芯片附接到第一芯片，使得散热材料位于第一芯片和第二芯片之间并且覆盖第一金属化系统的至少一部分。

    REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS
    3.
    发明申请
    REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS 审中-公开
    通过降低TRENCH电介质的污染，降低金属化层堆叠中的铁素体与低K材料的可变性

    公开(公告)号：US20130130498A1

    公开(公告)日：2013-05-23

    申请号：US13718644

    申请日：2012-12-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Frank Feustel ,  Thomas Werner ,  Michael Grillberger ,  Kai Frohberg

    IPC: H01L21/768

    CPC classification number: H01L21/76877 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Generally, the present disclosure is related to various techniques that may be used for forming metallization systems in a highly efficient manner by filling via openings and trenches in a common fill process, while reducing negative effects during the patterning of the via opening and the trenches. One illustrative method disclosed herein includes, among other things, forming a via opening in a first dielectric material of a metallization layer of a semiconductor device. Moreover, a second dielectric material is formed above the first dielectric material, wherein the second dielectric material fills the via opening. Furthermore, the method also includes forming a trench in the second dielectric material so as to connect to the via opening, and filling the trench and the via opening with a metal in a common fill process.

    Abstract translation: 通常，本公开涉及可以用于通过在公共填充过程中通过开口和沟槽填充而以高效方式形成金属化系统的各种技术，同时在通孔开口和沟槽的图案化期间减少负面影响。 本文公开的一种说明性方法尤其包括在半导体器件的金属化层的第一介电材料中形成通孔。 此外，第二电介质材料形成在第一电介质材料的上方，其中第二介电材料填充通孔。 此外，该方法还包括在第二电介质材料中形成沟槽，以便连接到通孔开口，并在通用填充工艺中用金属填充沟槽和通孔开口。

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