公开(公告)号：US20130154018A1

公开(公告)日：2013-06-20

申请号：US13769446

申请日：2013-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas Werner ,  Peter Baars ,  Frank Feustel

IPC: H01L23/538 ,  H01L27/088

CPC classification number: H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

Abstract translation: 本文公开了一种说明性的半导体器件，其包括具有漏极和源极区域以及栅电极结构的晶体管。 所公开的半导体器件还包括形成在第一电介质材料中的接触杆，所述接触杆连接到漏极和源极区域之一并且包括第一导电材料，所述接触棒沿晶体管的宽度方向延伸。 此外，说明性器件还包括形成在第二电介质材料中的导电线，该导电线包括具有沿晶体管的长度方向延伸的顶部宽度的上部，以及具有底部宽度延伸的下部 沿着所述长度方向小于所述上部的顶部宽度，其中所述导电线连接到所述接触杆并包括与所述第一导电材料不同的第二导电材料。

公开(公告)号：US20130084703A1

公开(公告)日：2013-04-04

申请号：US13687877

申请日：2012-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Frohberg ,  Frank Feustel ,  Thomas Werner

IPC: H01L21/02

CPC classification number: H01L21/02107 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/7843 ,  H01L29/785

Abstract: In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.

Abstract translation: 在复杂的半导体器件中，通过在对应的晶体管之间提供间隙或应力去耦合区域，可以在紧密堆积的器件区域的相邻晶体管元件之间实现有效的应力去耦合。 例如，可以在应力诱导材料中形成间隙，以便减小紧密间隔的晶体管元件上的应力诱导材料的相互作用。 在一些说明性方面，应力诱导材料可以作为每个单独的晶体管元件的岛来提供。

公开(公告)号：US20160111382A1

公开(公告)日：2016-04-21

申请号：US14519291

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Oliver Aubel ,  Georg Talut ,  Thomas Werner

IPC: H01L23/60 ,  H01L23/532

CPC classification number: H01L23/53214 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2224/05006 ,  H01L2224/05546

Abstract: The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Abstract translation: 本公开涉及包括布置在多个垂直级上的多条连接线的半导体结构，所述多条连接线至少包括布置在第一垂直级中的第一连接线和布置在第二垂直方向上的第二连接线 与第一垂直水平不同的防水层，以及放置在将第一连接线与第二连接线分隔开的垂直空间的至少一部分中的击穿防止层。

公开(公告)号：US20160111381A1

公开(公告)日：2016-04-21

申请号：US14515986

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Frank Feustel ,  Oliver Aubel

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L23/564 ,  H01L21/02118 ,  H01L21/768 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

Abstract translation: 半导体结构包括半导体衬底，设置在衬底上的一个或多个互连层和电路。 电路包括形成在基板上的多个电路元件和设置在一个或多个互连层中的多个电连接。 在一个或多个互连层中提供模具密封。 模密封泄漏检测材料布置在模具密封件和多个电连接件之间的一个或多个互连层中。 如果模具密封件是完整的，模具密封件可保护模具密封件泄漏检测材料免受潮湿。 模封密封泄漏检测材料适于在模具密封泄漏检测材料暴露于水分之后提供电路的可检测的修改。

公开(公告)号：US09627317B2

公开(公告)日：2017-04-18

申请号：US15137740

申请日：2016-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Oliver Aubel ,  Frank Feustel

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/58 ,  H01L23/532 ,  H01L25/065 ,  H01L21/288 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

公开(公告)号：US09455232B2

公开(公告)日：2016-09-27

申请号：US14515986

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Frank Feustel ,  Oliver Aubel

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/02 ,  H01L21/66 ,  H01L23/58 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/564 ,  H01L21/02118 ,  H01L21/768 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

Abstract translation: 半导体结构包括半导体衬底，设置在衬底上的一个或多个互连层和电路。 电路包括形成在基板上的多个电路元件和设置在一个或多个互连层中的多个电连接。 在一个或多个互连层中提供模具密封。 模密封泄漏检测材料布置在模具密封件和多个电连接件之间的一个或多个互连层中。 如果模具密封件是完整的，模具密封件可保护模具密封件泄漏检测材料免受潮湿。 模封密封泄漏检测材料适于在模具密封泄漏检测材料暴露于水分之后提供电路的可检测的修改。

公开(公告)号：US20160190104A1

公开(公告)日：2016-06-30

申请号：US15064755

申请日：2016-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/00014

Abstract: In a method of forming a three-dimensional semiconductor device, a first chip is provided that includes a first substrate, a first device layer positioned on and covering the first substrate, and a first metallization system positioned on and covering the first device layer, wherein the first device layer includes a plurality of first transistor elements. A second chip is also provided and includes a second substrate, a second device layer positioned on and covering the second substrate, and a second metallization system positioned on and covering the second device layer, wherein the second device layer includes a plurality of second transistor elements. The second chip is attached to the first chip so that a heat spreading material is positioned between the first chip and the second chip and covers at least a portion of the first metallization system.

Abstract translation: 在形成三维半导体器件的方法中，提供了第一芯片，其包括第一衬底，位于第一衬底上并覆盖第一衬底的第一器件层，以及位于第一器件层上并覆盖第一器件层的第一金属化系统，其中 第一器件层包括多个第一晶体管元件。 还提供了第二芯片，并且包括第二衬底，位于第二衬底上并覆盖第二衬底的第二器件层，以及位于第二器件层上并覆盖第二器件层的第二金属化系统，其中第二器件层包括多个第二晶体管元件 。 第二芯片附接到第一芯片，使得散热材料位于第一芯片和第二芯片之间并且覆盖第一金属化系统的至少一部分。

公开(公告)号：US20160079116A1

公开(公告)日：2016-03-17

申请号：US14487250

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Oliver Aubel ,  Frank Feustel

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/56 ,  H01L27/02

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

Abstract translation: 提供一种半导体晶片，其包括多个管芯，所述多个管芯中的每一个包括多个半导体器件，多个管芯密封件，所述多个管芯密封件中的每一个形成在所述多个管芯中的一个的周边， 以及多个导电连接件，所述多个导电连接中的每一个将所述多个模具密封件中的一个与所述多个模具密封件中的另一个连接。

公开(公告)号：US10014279B2

公开(公告)日：2018-07-03

申请号：US15064755

申请日：2016-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/00014

Abstract: In a method of forming a three-dimensional semiconductor device, a first chip is provided that includes a first substrate, a first device layer positioned on and covering the first substrate, and a first metallization system positioned on and covering the first device layer, wherein the first device layer includes a plurality of first transistor elements. A second chip is also provided and includes a second substrate, a second device layer positioned on and covering the second substrate, and a second metallization system positioned on and covering the second device layer, wherein the second device layer includes a plurality of second transistor elements. The second chip is attached to the first chip so that a heat spreading material is positioned between the first chip and the second chip and covers at least a portion of the first metallization system.

公开(公告)号：US09349641B2

公开(公告)日：2016-05-24

申请号：US14487250

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Oliver Aubel ,  Frank Feustel

IPC: H01L21/44 ,  H01L21/768 ,  H01L27/02 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

Abstract translation: 提供一种半导体晶片，其包括多个管芯，所述多个管芯中的每一个包括多个半导体器件，多个管芯密封件，所述多个管芯密封件中的每一个形成在所述多个管芯中的一个的周边， 以及多个导电连接件，所述多个导电连接中的每一个将所述多个模具密封件中的一个与所述多个模具密封件中的另一个连接。