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    SEMICONDUCTOR STRUCTURE INCLUDING A DIE SEAL LEAKAGE DETECTION MATERIAL, METHOD FOR THE FORMATION THEREOF AND METHOD INCLUDING A TEST OF A SEMICONDUCTOR STRUCTURE
    1.
    发明申请
    SEMICONDUCTOR STRUCTURE INCLUDING A DIE SEAL LEAKAGE DETECTION MATERIAL, METHOD FOR THE FORMATION THEREOF AND METHOD INCLUDING A TEST OF A SEMICONDUCTOR STRUCTURE 有权
    包括DIE密封泄漏检测材料的半导体结构及其形成方法和包括半导体结构测试的方法

    公开(公告)号：US20160111381A1

    公开(公告)日：2016-04-21

    申请号：US14515986

    申请日：2014-10-16

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Thomas Werner ,  Frank Feustel ,  Oliver Aubel

    IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/31

    CPC classification number: H01L23/564 ,  H01L21/02118 ,  H01L21/768 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

    Abstract translation: 半导体结构包括半导体衬底，设置在衬底上的一个或多个互连层和电路。 电路包括形成在基板上的多个电路元件和设置在一个或多个互连层中的多个电连接。 在一个或多个互连层中提供模具密封。 模密封泄漏检测材料布置在模具密封件和多个电连接件之间的一个或多个互连层中。 如果模具密封件是完整的，模具密封件可保护模具密封件泄漏检测材料免受潮湿。 模封密封泄漏检测材料适于在模具密封泄漏检测材料暴露于水分之后提供电路的可检测的修改。

    SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT BARS AND METAL LINES WITH INCREASED VIA LANDING REGIONS
    2.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT BARS AND METAL LINES WITH INCREASED VIA LANDING REGIONS 有权
    包含自对准接触棒和金属线的半导体器件通过着陆区域增加

    公开(公告)号：US20130154018A1

    公开(公告)日：2013-06-20

    申请号：US13769446

    申请日：2013-02-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Thomas Werner ,  Peter Baars ,  Frank Feustel

    IPC: H01L23/538 ,  H01L27/088

    CPC classification number: H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

    Abstract translation: 本文公开了一种说明性的半导体器件，其包括具有漏极和源极区域以及栅电极结构的晶体管。 所公开的半导体器件还包括形成在第一电介质材料中的接触杆，所述接触杆连接到漏极和源极区域之一并且包括第一导电材料，所述接触棒沿晶体管的宽度方向延伸。 此外，说明性器件还包括形成在第二电介质材料中的导电线，该导电线包括具有沿晶体管的长度方向延伸的顶部宽度的上部，以及具有底部宽度延伸的下部 沿着所述长度方向小于所述上部的顶部宽度，其中所述导电线连接到所述接触杆并包括与所述第一导电材料不同的第二导电材料。

    REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS
    7.
    发明申请
    REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS 审中-公开
    通过降低TRENCH电介质的污染，降低金属化层堆叠中的铁素体与低K材料的可变性

    公开(公告)号：US20130130498A1

    公开(公告)日：2013-05-23

    申请号：US13718644

    申请日：2012-12-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Frank Feustel ,  Thomas Werner ,  Michael Grillberger ,  Kai Frohberg

    IPC: H01L21/768

    CPC classification number: H01L21/76877 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Generally, the present disclosure is related to various techniques that may be used for forming metallization systems in a highly efficient manner by filling via openings and trenches in a common fill process, while reducing negative effects during the patterning of the via opening and the trenches. One illustrative method disclosed herein includes, among other things, forming a via opening in a first dielectric material of a metallization layer of a semiconductor device. Moreover, a second dielectric material is formed above the first dielectric material, wherein the second dielectric material fills the via opening. Furthermore, the method also includes forming a trench in the second dielectric material so as to connect to the via opening, and filling the trench and the via opening with a metal in a common fill process.

    Abstract translation: 通常，本公开涉及可以用于通过在公共填充过程中通过开口和沟槽填充而以高效方式形成金属化系统的各种技术，同时在通孔开口和沟槽的图案化期间减少负面影响。 本文公开的一种说明性方法尤其包括在半导体器件的金属化层的第一介电材料中形成通孔。 此外，第二电介质材料形成在第一电介质材料的上方，其中第二介电材料填充通孔。 此外，该方法还包括在第二电介质材料中形成沟槽，以便连接到通孔开口，并在通用填充工艺中用金属填充沟槽和通孔开口。

    METHODS OF FORMING 3-D INTEGRATED SEMICONDUCTOR DEVICES HAVING INTERMEDIATE HEAT SPREADING CAPABILITIES
    10.
    发明申请
    METHODS OF FORMING 3-D INTEGRATED SEMICONDUCTOR DEVICES HAVING INTERMEDIATE HEAT SPREADING CAPABILITIES 有权
    形成具有中间热传递能力的3-D集成半导体器件的方法

    公开(公告)号：US20160190104A1

    公开(公告)日：2016-06-30

    申请号：US15064755

    申请日：2016-03-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Thomas Werner ,  Michael Grillberger ,  Frank Feustel

    IPC: H01L25/065 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: In a method of forming a three-dimensional semiconductor device, a first chip is provided that includes a first substrate, a first device layer positioned on and covering the first substrate, and a first metallization system positioned on and covering the first device layer, wherein the first device layer includes a plurality of first transistor elements. A second chip is also provided and includes a second substrate, a second device layer positioned on and covering the second substrate, and a second metallization system positioned on and covering the second device layer, wherein the second device layer includes a plurality of second transistor elements. The second chip is attached to the first chip so that a heat spreading material is positioned between the first chip and the second chip and covers at least a portion of the first metallization system.

    Abstract translation: 在形成三维半导体器件的方法中，提供了第一芯片，其包括第一衬底，位于第一衬底上并覆盖第一衬底的第一器件层，以及位于第一器件层上并覆盖第一器件层的第一金属化系统，其中 第一器件层包括多个第一晶体管元件。 还提供了第二芯片，并且包括第二衬底，位于第二衬底上并覆盖第二衬底的第二器件层，以及位于第二器件层上并覆盖第二器件层的第二金属化系统，其中第二器件层包括多个第二晶体管元件 。 第二芯片附接到第一芯片，使得散热材料位于第一芯片和第二芯片之间并且覆盖第一金属化系统的至少一部分。

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