公开(公告)号：US20160111374A1

公开(公告)日：2016-04-21

申请号：US14887984

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc. ,  ZEON CORPORATION

Inventor： Markus Brink ,  Robert L. Bruce ,  Sebastian U. Engelmann ,  Nicholas C. M. Fuller ,  Hiroyuki Miyazoe ,  Masahiro Nakamura

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53295 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.

公开(公告)号：US09633948B2

公开(公告)日：2017-04-25

申请号：US14887984

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc. ,  ZEON CORPORATION

Inventor： Markus Brink ,  Robert L. Bruce ,  Sebastian U. Engelmann ,  Nicholas C. M. Fuller ,  Hiroyuki Miyazoe ,  Masahiro Nakamura

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.

公开(公告)号：US09263393B2

公开(公告)日：2016-02-16

申请号：US14711872

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cyril Cabral, Jr. ,  Benjamin L. Fletcher ,  Nicholas C. M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/535 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8238

CPC classification number: H01L23/535 ,  H01L21/02109 ,  H01L21/31111 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.