公开(公告)号：US09299639B2

公开(公告)日：2016-03-29

申请号：US13734524

申请日：2013-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cyril Cabral, Jr. ,  Sebastian U. Engelmann ,  Benjamin L. Fletcher ,  Michael S. Gordon ,  Eric A. Joseph

IPC: H01L23/48 ,  H01L29/45 ,  H01L21/768 ,  H01L23/532 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L23/48 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer line widths, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract translation: 集成电路包括多个半导体器件和连接半导体器件的多条导线，其中导线包括沉积在过渡金属上的过渡金属和保护帽。 或者，集成电路包括多个半导体器件和连接半导体器件并具有八十纳米间距的多条导线，其中导电线包括沉积在过渡金属上的过渡金属和保护帽，其中保护性 帽的厚度在约5至15纳米之间。 或者，集成电路包括多个半导体器件和连接半导体器件并具有八十纳米线宽的多条导线，其中导电线包括沉积在过渡金属上的过渡金属和保护帽，其中， 保护帽的厚度介于约5至15纳米之间。

公开(公告)号：US09299638B2

公开(公告)日：2016-03-29

申请号：US13707003

申请日：2012-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cyril Cabral, Jr. ,  Sebastian U. Engelmann ,  Benjamin L. Fletcher ,  Michael S. Gordon ,  Eric A. Joseph

IPC: H01L21/4763 ,  H01L23/48 ,  H01L29/45 ,  H01L21/768 ,  H01L23/532 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L23/48 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract translation: 在集成电路中制造导线包括图案化过渡金属层以形成导电线并且在一个或多个导电线中的至少一些导电线上沉积保护盖。 或者，在集成电路中制造导线包括图案化过渡金属层以形成导电线，其中导线具有八十纳米的间距，并且在至少一些导电线上沉积保护盖，其中， 保护帽的厚度介于约5至15纳米之间。 或者，在集成电路中制造导线包括图案化过渡金属层以形成导电线，其中导线具有八十纳米线宽，并且在至少一些导电线上沉积保护盖，其中 保护帽的厚度在大约5至15纳米之间。

公开(公告)号：US09490202B2

公开(公告)日：2016-11-08

申请号：US14505087

申请日：2014-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/00 ,  H01L23/522 ,  H01L23/482 ,  H01L23/528 ,  H01L23/00 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/31127 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/4821 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material, Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

Abstract translation: 用于形成自对准气隙互连结构的装置和方法包括将导电层蚀刻到衬底以形成具有图案化间隙的导电结构并用牺牲材料填充间隙。 将牺牲材料平坦化以暴露导电层的顶表面。 在导电结构和牺牲材料上沉积可渗透盖层，通过可渗透层去除牺牲材料形成自对准气囊。

公开(公告)号：US09263393B2

公开(公告)日：2016-02-16

申请号：US14711872

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cyril Cabral, Jr. ,  Benjamin L. Fletcher ,  Nicholas C. M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/535 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8238

CPC classification number: H01L23/535 ,  H01L21/02109 ,  H01L21/31111 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.