公开(公告)号：US09230637B1

公开(公告)日：2016-01-05

申请号：US14481384

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shahid Ahmad Butt ,  Pamela Castalino ,  Harold Pilo

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418

Abstract: Transistors are connected to ground outside of an SRAM array column. One transistor is connected from VSS to ground on the Q side of an SRAM cell. Another transistor is connected from VSS to ground on the Q′ (Q complement) side of an SRAM cell. Each transistor is gated by is complementary bit line. The Q side transistor is gated by the BL′ (bit line complement, or “BLC”) line, and the Q′ side is gated by the BL line. The ground of the complement side is disconnected during a write operation to increase the performance of a state change during a write operation where a logical one is written to the Q node, thus improving write margin.

Abstract translation: 晶体管连接到SRAM阵列列的外部。 在SRAM单元的Q侧，一个晶体管从VSS连接到地。 在SRAM单元的Q'（Q补码）侧，另一个晶体管从VSS连接到地。 每个晶体管都是互补的位线。 Q侧晶体管由BL'（位线补码或“BLC”）线选通，Q'侧由BL线选通。 在写入操作期间补码侧的接地断开以增加写入操作期间的状态改变的性能，其中将逻辑1写入Q节点，从而提高写入裕度。

公开(公告)号：US09355739B2

公开(公告)日：2016-05-31

申请号：US14084644

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pamela Castalino ,  Toshiaki Kirihata ,  Derek H. Leu

IPC: G11C11/56 ,  G11C16/04 ,  G11C17/18 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C17/18 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices. The bitline circuits having mode and bank access dependent bitline circuit further enables a single device memory array, by using two arrays, wherein said one of the array is used for reference to the other array using an open bitline architecture.

Abstract translation: 嵌入式多时间只读存储器的位线电路，包括耦合到每行中的多个字线，每列中的位线和源极线的多个NMOS存储器单元。 更具体地，位线电路通过模式相关的位线下拉电路来控制目标NMOS存储器阵列的电荷陷阱行为，从而将位线强烈地放电到GND，以在编程模式下有效地捕获电荷，并将位线弱化 GND产生位线电压以检测电荷陷阱状态。 模式相关电路通过使用至少两个NMOS来切换器件强度，使用读取模式下的脉冲栅极控制或使用模拟电压来限制位线电流来实现。 所提出的方法还包括保护装置，允许使用薄氧化物装置的所有位线控制电路。 具有模式和与银行接入相关的位线电路的位线电路还通过使用两个阵列使单个设备存储器阵列进一步启用，其中阵列中的所述一个使用打开的位线架构用于引用另一阵列。