公开(公告)号：US10121702B1

公开(公告)日：2018-11-06

申请号：US15638087

申请日：2017-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Min Gyu Sung ,  Ruilong Xie ,  Puneet H. Suvarna

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535

Abstract: At least one method, apparatus and system disclosed herein involves performing an early-process of source/drain (S/D) contact cut and S/D contact etch steps for manufacturing a finFET device. A gate structure, a source structure, and a drain structure of a transistor are formed. The gate structure comprises a dummy gate region, a gate spacer, and a liner. A source/drain (S/D) contact cut process is performed. An S/D contact etch process is performed. A replacement metal gate (RMG) process is performed subsequent to performing the S/D contact etch process. An S/D contact metallization process is performed.

公开(公告)号：US20180366372A1

公开(公告)日：2018-12-20

申请号：US15626321

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet H. Suvarna ,  Steven Bentley ,  Mark V. Raymond ,  Peter M. Zeitzoff

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/45 ,  H01L29/78 ,  H01L29/08

Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.

公开(公告)号：US10157794B1

公开(公告)日：2018-12-18

申请号：US15626321

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet H. Suvarna ,  Steven Bentley ,  Mark V. Raymond ,  Peter M. Zeitzoff

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/45 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423

Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.

公开(公告)号：US20190319180A1

公开(公告)日：2019-10-17

申请号：US16448544

申请日：2019-06-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Philipp Steinmann ,  Puneet H. Suvarna

IPC: H01L35/32 ,  H01L35/22 ,  H01L35/34

Abstract: Structures that include semiconductor fins and methods for forming a structure that includes semiconductor fins. A first fin comprised of n-type semiconductor material and a second fin comprised of p-type semiconductor material are formed. A conductive strap is formed that couples an end of the first fin with an end of the second fin

公开(公告)号：US10236292B1

公开(公告)日：2019-03-19

申请号：US16156082

申请日：2018-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet H. Suvarna ,  Hiroaki Niimi ,  Steven J. Bentley ,  Ali Razavieh

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  H01L29/45 ,  H01L29/786

Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.

公开(公告)号：US10256158B1

公开(公告)日：2019-04-09

申请号：US15820477

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Steven Bentley ,  Puneet H. Suvarna

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/167 ,  H01L29/423 ,  H01L27/092 ,  H01L21/822 ,  H01L29/161 ,  H01L21/84

Abstract: Integrated circuit structures include isolation elements extending into a substrate, and source/drain regions of a first transistor contacting the isolation elements. The isolation elements extend from the substrate to the source/drain regions of the first transistor. Isolation layers contact the source/drain regions of the first transistor, and source/drain regions of a second transistor also contact the isolation layers. Thus, the isolation layers are between the source/drain regions of the first transistor and the source/drain regions of the second transistor. Channel regions of the first transistor contact and extend between the source/drain regions of the first transistor, and channel regions of the second transistor contact and extend between the source/drain regions of the second transistor. A gate conductor surrounds sides of the channel region of the first transistor and the channel region of the second transistor.

公开(公告)号：US10192867B1

公开(公告)日：2019-01-29

申请号：US15888401

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet H. Suvarna ,  Hiroaki Niimi ,  Steven J. Bentley ,  Ali Razavieh

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/285

Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.

公开(公告)号：US20180342661A1

公开(公告)日：2018-11-29

申请号：US15605289

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Philipp Steinmann ,  Puneet H. Suvarna

IPC: H01L35/32 ,  H01L35/22 ,  H01L35/34

Abstract: Structures that include semiconductor fins and methods for forming a structure that includes semiconductor fins. A first fin comprised of n-type semiconductor material and a second fin comprised of p-type semiconductor material are formed. A conductive strap is formed that couples an end of the first fin with an end of the second fin.