公开(公告)号：US20140217544A1

公开(公告)日：2014-08-07

申请号：US13761686

申请日：2013-02-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ram Asra

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66651 ,  H01L29/66772

Abstract: One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在体半导体衬底的隔离区域内形成沟槽，在沟槽中形成绝缘材料的区域，并在沟槽内部和绝缘材料区域的上表面上方形成半导体材料。 本文公开的衬底包括体半导体衬底中的隔离衬底区域，位于限定在隔离衬底区域中的沟槽内的绝缘材料的区域和位于沟槽内并位于沟槽的上表面之上的半导体材料 绝缘材料。

公开(公告)号：US20180358272A1

公开(公告)日：2018-12-13

申请号：US15622061

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mitsuhiro Togo ,  Ram Asra ,  Xing Zhang ,  Palanivel Balasubramaniam

IPC: H01L21/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L22/20 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/42376

Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.

公开(公告)号：US08921188B2

公开(公告)日：2014-12-30

申请号：US13761686

申请日：2013-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ram Asra

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66651 ,  H01L29/66772

Abstract: One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在体半导体衬底的隔离区域内形成沟槽，在沟槽中形成绝缘材料的区域，并在沟槽内部和绝缘材料区域的上表面上方形成半导体材料。 本文公开的衬底包括体半导体衬底中的隔离衬底区域，位于限定在隔离衬底区域中的沟槽内的绝缘材料的区域和位于沟槽内并位于沟槽的上表面之上的半导体材料 绝缘材料。

公开(公告)号：US10373942B2

公开(公告)日：2019-08-06

申请号：US15829459

申请日：2017-12-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ram Asra ,  Mohit Bajaj ,  Edward Nowak ,  Kota V. R. M. Murali

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L27/11 ,  H01L29/06 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/423

Abstract: A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.

公开(公告)号：US10325824B2

公开(公告)日：2019-06-18

申请号：US15622061

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mitsuhiro Togo ,  Ram Asra ,  Xing Zhang ,  Palanivel Balasubramaniam

IPC: H01L21/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.