公开(公告)号：US10295592B2

公开(公告)日：2019-05-21

申请号：US15621529

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Jeanne P. Bickford ,  Paul J. Grzymkowski ,  Susan K. Lichtensteiger ,  Robert J. McMahon ,  Troy J. Perry ,  David M. Picozzi ,  Thomas G. Sopchak

IPC: G01R31/28 ,  G01R21/133 ,  G06F17/50 ,  G01R31/317

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

公开(公告)号：US09759767B2

公开(公告)日：2017-09-12

申请号：US14695112

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Jeanne P. Bickford ,  Paul J. Grzymkowski ,  Susan K. Lichtensteiger ,  Robert J. McMahon ,  Troy J. Perry ,  David M. Picozzi ,  Thomas G. Sopchak

IPC: G01R31/00 ,  G01R31/28 ,  G01R21/133 ,  G06F17/50 ,  G01R31/317

CPC classification number: G01R31/2894 ,  G01R21/133 ,  G01R31/31718 ,  G06F17/5045 ,  G06F2217/78

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

公开(公告)号：US09653330B1

公开(公告)日：2017-05-16

申请号：US15015535

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  John R. Goss ,  Robert J. McMahon ,  Troy J. Perry ,  Thomas G. Sopchak

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/66 ,  G06F17/50 ,  G01R31/317

CPC classification number: G01R31/31718 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34

Abstract: Disclosed are methods for performing threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning (SVB) to improve SVB accuracy and, thereby product yield and reliability. In the methods, a process distribution for an integrated circuit chip design is divided into process windows, each associated with a corresponding performance range and a corresponding minimum supply voltage. First performance measurements are acquired from first performance monitors associated with first transistors on chips manufactured according to the design. Based on the first performance measurements, the chips are assigned to groups corresponding to the process windows. Second performance measurements are also be acquired from second performance monitors associated with second transistors, which are on the chips and which have either a different VT-type or a different maximum fan-out than the first transistors. Based on the second performance measurements, a determination is made as to whether chip group reassignment is warranted.

公开(公告)号：US20170276726A1

公开(公告)日：2017-09-28

申请号：US15621529

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Jeanne P. Bickford ,  Paul J. Grzymkowski ,  Susan K. Lichtensteiger ,  Robert J. McMahon ,  Troy J. Perry ,  David M. Picozzi ,  Thomas G. Sopchak

IPC: G01R31/28 ,  G01R21/133 ,  G01R31/317 ,  G06F17/50

CPC classification number: G01R31/2894 ,  G01R21/133 ,  G01R31/31718 ,  G06F17/5045 ,  G06F2217/78

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.