公开(公告)号：US09760673B2

公开(公告)日：2017-09-12

申请号：US15012331

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric D. Hunt-Schroeder ,  John R. Goss ,  Igor Arsovski ,  Paul J. Grzymkowski

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/64

Abstract: Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

公开(公告)号：US20170220727A1

公开(公告)日：2017-08-03

申请号：US15012331

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric D. Hunt-Schroeder ,  John R. Goss ,  Igor Arsovski ,  Paul J. Grzymkowski

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/64

Abstract: Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

公开(公告)号：US09653330B1

公开(公告)日：2017-05-16

申请号：US15015535

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  John R. Goss ,  Robert J. McMahon ,  Troy J. Perry ,  Thomas G. Sopchak

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/66 ,  G06F17/50 ,  G01R31/317

CPC classification number: G01R31/31718 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34

Abstract: Disclosed are methods for performing threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning (SVB) to improve SVB accuracy and, thereby product yield and reliability. In the methods, a process distribution for an integrated circuit chip design is divided into process windows, each associated with a corresponding performance range and a corresponding minimum supply voltage. First performance measurements are acquired from first performance monitors associated with first transistors on chips manufactured according to the design. Based on the first performance measurements, the chips are assigned to groups corresponding to the process windows. Second performance measurements are also be acquired from second performance monitors associated with second transistors, which are on the chips and which have either a different VT-type or a different maximum fan-out than the first transistors. Based on the second performance measurements, a determination is made as to whether chip group reassignment is warranted.