公开(公告)号：US20150123214A1

公开(公告)日：2015-05-07

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。

公开(公告)号：US09105507B2

公开(公告)日：2015-08-11

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。

公开(公告)号：US08969932B2

公开(公告)日：2015-03-03

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。

公开(公告)号：US20140159126A1

公开(公告)日：2014-06-12

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。

公开(公告)号：US20160358851A1

公开(公告)日：2016-12-08

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US09576894B2

公开(公告)日：2017-02-21

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US09362162B2

公开(公告)日：2016-06-07

申请号：US14459444

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Teck Jung Tang ,  Mark Alexander Zaleski

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).

Abstract translation: 提供了用于制造用于例如为电路结构提供BEOL互连的层间结构的方法。 该方法包括例如提供层间结构，包括：在衬底结构之上提供未固化的绝缘层; 在未固化的绝缘层上形成能量去除膜; 通过所述能量去除膜形成至少一个开口并且至少部分地延伸到所述未固化的绝缘层中; 并施加能量以固化未固化绝缘层，建立固化绝缘层，并部分分解能量去除膜，在固化绝缘层上形成厚度减小的能量去除膜，包括固化绝缘层的层间结构，以及 施加减小一个开口的纵横比的能量。 在一个实施方案中，未固化的绝缘层包括在施加能量的同时分解部分以进一步改善纵横比的致孔剂。

公开(公告)号：US09142451B2

公开(公告)日：2015-09-22

申请号：US14027479

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Matthew Herrick ,  Teck Jung Tang ,  Dewei Xu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.

Abstract translation: 提供具有降低的介电常数的层间制造方法和层间结构。 所述方法包括例如：提供具有可蒸发材料的第一未固化绝缘层; 以及在第一未固化绝缘层上设置具有致孔剂的第二未固化绝缘层。 层间结构包括第一绝缘层和第二绝缘层，并且所述方法还包括固化层间结构，在第一绝缘层中留下空气间隙，以及空气间隙大于孔的第二绝缘层中的孔，以及 其中气隙和气孔降低了层间结构的介电常数。