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    PUNCH-THROUGH-STOP AFTER PARTIAL FIN ETCH
    1.
    发明申请
    PUNCH-THROUGH-STOP AFTER PARTIAL FIN ETCH 有权
    部分FIN ETCH后的PUNCH-THROUGH-STOP

    公开(公告)号：US20160307807A1

    公开(公告)日：2016-10-20

    申请号：US14691233

    申请日：2015-04-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kwan-Yong LIM ,  Steven John BENTLEY ,  Chanro PARK

    IPC: H01L21/8238 ,  H01L21/225 ,  H01L29/10 ,  H01L21/308 ,  H01L29/167 ,  H01L21/324

    CPC classification number: H01L21/823821 ,  H01L21/2253 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1083

    Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).

    Abstract translation: 减少由于短路效应引起的三维半导体器件漏电的方法包括提供起始半导体结构，该结构包括具有n型器件区域和p型器件区域的半导体衬底，p型 器件区域，其包括p型半导体材料的上层，两个区域上的硬掩模层，以及用于在每个区域中构图至少一个翅片的结构上的掩模。 该方法还包括在起始半导体结构的每个区域中形成部分散热片，在该结构上形成共形衬垫，在每个区域中产生穿通停止（PTS），使得每个PTS扩散穿过顶部 并且从部分翅片在每个区域中产生全鳍。

    FIN PITCH SCALING AND ACTIVE LAYER ISOLATION
    2.
    发明申请
    FIN PITCH SCALING AND ACTIVE LAYER ISOLATION 有权
    FIN PITCH SCALING和主动层隔离

    公开(公告)号：US20150061014A1

    公开(公告)日：2015-03-05

    申请号：US14011125

    申请日：2013-08-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil JACOB ,  Murat Kerem AKARVARDAR ,  Steven John BENTLEY ,  Bartlomiej Jan PAWLAK

    IPC: H01L21/764 ,  H01L21/02 ,  H01L29/78

    CPC classification number: H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

    Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

    Abstract translation: 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。

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