公开(公告)号：US20150340471A1

公开(公告)日：2015-11-26

申请号：US14286400

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong LIM ,  Jody FRONHEISER ,  Christopher PRINDLE

IPC: H01L29/66 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.

Abstract translation: 提供通过部分EPI生长形成凸起S / D区域的方法，其中部分EPI衬垫在其间，并且提供所得到的装置。 实施例包括形成在STI层上延伸的翅片组; 在翅片组上形成一个门; 在栅极的每一侧上形成栅极间隔物; 在所述翅片组的每个翅片上形成靠近每个间隔件的凸起S / D区域，每个凸起的S / D区域具有顶表面，垂直侧壁和下表面; 在每个凸起的S / D区域之间和之间形成衬垫; 从每个凸起的S / D区域的顶表面和一组翅片之间移除衬垫; 在每个凸起的S / D区域的上表面上形成过度生长区域; 在升高的S / D区域之间形成ILD; 并通过ILD形成接触，直到升高的S / D区域。

公开(公告)号：US20160204265A1

公开(公告)日：2016-07-14

申请号：US15077153

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Kwan-Yong LIM ,  Sukwon HONG

IPC: H01L29/78 ,  H01L21/225 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract translation: 提供了制造包括FinFET结构的电路结构的方法，包括：提供衬底和在衬底上方具有第一阈值电压的第一材料以及具有低于第一材料之上的第一阈值电压的第二阈值电压的第二材料; 形成具有由所述第一材料形成的基部翅片部分和由所述第二材料形成的上部翅片部分的翅片; 在所述翅片上提供栅极结构以形成一个或多个FinFET结构，其中所述栅极结构至少缠绕在所述上鳍部分上并具有低于所述第一阈值电压并高于所述第二阈值电压的工作电压，使得所述上翅片 部分限定一个或多个FinFET结构的通道尺寸。 还提供了包括FinFET结构的电路结构，其中FinFET结构具有仅由其上翅部分限定的均匀通道尺寸。

公开(公告)号：US20190229183A1

公开(公告)日：2019-07-25

申请号：US15875132

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Hui ZANG ,  Chun Yu WONG ,  Kwan-Yong LIM

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762

Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

公开(公告)号：US20160307807A1

公开(公告)日：2016-10-20

申请号：US14691233

申请日：2015-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kwan-Yong LIM ,  Steven John BENTLEY ,  Chanro PARK

IPC: H01L21/8238 ,  H01L21/225 ,  H01L29/10 ,  H01L21/308 ,  H01L29/167 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/2253 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1083

Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).

Abstract translation: 减少由于短路效应引起的三维半导体器件漏电的方法包括提供起始半导体结构，该结构包括具有n型器件区域和p型器件区域的半导体衬底，p型 器件区域，其包括p型半导体材料的上层，两个区域上的硬掩模层，以及用于在每个区域中构图至少一个翅片的结构上的掩模。 该方法还包括在起始半导体结构的每个区域中形成部分散热片，在该结构上形成共形衬垫，在每个区域中产生穿通停止（PTS），使得每个PTS扩散穿过顶部 并且从部分翅片在每个区域中产生全鳍。

公开(公告)号：US20170373071A1

公开(公告)日：2017-12-28

申请号：US15193902

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong LIM ,  Motoi ICHIHASHI ,  Youngtag WOO ,  Deepak NAYAK

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: A semiconductor memory structure includes adjacent cross-sectionally rectangular-shaped bottom source and drain electrodes, the electrodes including n-type electrode(s) and p-type electrode(s), and vertical channel transistors on one or more of the n-type electrode(s) and one or more of the p-type electrode(s); each vertical channel transistor including a vertical channel and a gate electrode wrapped therearound, some of the transistors including pull-up transistors. The semiconductor memory structure further includes a routing gate electrode for each gate electrode, and a shared contact having at least two parts, each part situated over the routing gate electrodes for the pull-up transistors. A unit semiconductor memory cell, the semiconductor memory structure and a corresponding method of forming the memory structure are also provided.

公开(公告)号：US20170358687A1

公开(公告)日：2017-12-14

申请号：US15180422

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kwan-Yong LIM ,  Steven John BENTLEY ,  Daniel CHANEMOUGAME

IPC: H01L29/786 ,  H01L27/24 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/265 ,  H01L21/30604 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/7926 ,  H01L2029/7858

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

公开(公告)号：US20160071932A1

公开(公告)日：2016-03-10

申请号：US14480974

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Kwan-Yong LIM ,  Sukwon HONG

IPC: H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

公开(公告)号：US20190027483A1

公开(公告)日：2019-01-24

申请号：US16056660

申请日：2018-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Manfred ELLER ,  Kwan-Yong LIM

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

公开(公告)号：US20190019880A1

公开(公告)日：2019-01-17

申请号：US15649227

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Seong Yeol MUN ,  Kwan-Yong LIM ,  Kijik LEE

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.

公开(公告)号：US20180061993A1

公开(公告)日：2018-03-01

申请号：US15793545

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki NIIMI ,  Kwan-Yong LIM ,  Steven John BENTLEY ,  Daniel CHANEMOUGAME

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L27/24 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/265 ,  H01L21/30604 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/7926 ,  H01L2029/7858

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.