公开(公告)号：US10186482B2

公开(公告)日：2019-01-22

申请号：US14975726

申请日：2015-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Junjing Bao ,  Samuel S. Choi ,  Wai-kin Li

IPC: H01L23/525 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second via opening is self-aligned to a second trench in the substrate, a portion of the second via opening overlaps a portion of the first via opening to form an overlap region, and the overlap region having a width (w) equal to or greater than a space (s) between the first trench and the second trench, and removing a portion of the substrate in the overlap region to form a bridge opening, the bridge opening is adjacent to the first and second via openings and extends between the first and second trenches.

公开(公告)号：US20160104677A1

公开(公告)日：2016-04-14

申请号：US14975726

申请日：2015-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Junjing Bao ,  Samuel S. Choi ,  Wai-kin Li

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second via opening is self-aligned to a second trench in the substrate, a portion of the second via opening overlaps a portion of the first via opening to form an overlap region, and the overlap region having a width (w) equal to or greater than a space (s) between the first trench and the second trench, and removing a portion of the substrate in the overlap region to form a bridge opening, the bridge opening is adjacent to the first and second via openings and extends between the first and second trenches.

Abstract translation: 一种方法，包括在衬底中形成第一通孔，所述第一通孔开口与所述衬底中的第一沟槽自对准，在所述衬底中形成第二通孔，所述第二通孔开口自对准至第二沟槽， 所述第二通孔开口的一部分与所述第一通路孔的一部分重叠以形成重叠区域，并且所述重叠区域的宽度（w）等于或大于所述第一沟槽和所述第二通路孔之间的空间 并且在所述重叠区域中移除所述基板的一部分以形成桥开口，所述桥开口与所述第一和第二通孔相邻，并且在所述第一沟槽和所述第二沟槽之间延伸。

公开(公告)号：US09312191B2

公开(公告)日：2016-04-12

申请号：US14459407

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-kin Li

IPC: H01L21/02 ,  H01L21/84 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/823821 ,  H01L21/823857

Abstract: A method of reducing etch time needed for patterning an organic planarization layer (OPL) in a block mask stack so as to minimize damages to gate structures and fin structures in a block mask patterning process is provided. The block mask stack including an OPL, a developable antireflective coating (DARC) layer atop the OPL and a photoresist layer atop the DARC layer is employed to mask one conductivity type of FinFET while exposing the other conductivity type FinFET during source/drain ion implantation. The OPL is configured to have a minimum thickness sufficient to fill in spaces between semiconductor fins and to cover the semiconductor fins. The DARC layer is configured to planarize topography of semiconductor fins so as to provide a planar top surface for the ensuing lithography and etch processes.

Abstract translation: 提供了一种减少在块掩模层中构图有机平坦化层（OPL）所需蚀刻时间的方法，以便在块掩模图案化工艺中对栅极结构和鳍结构的损害最小化。 包括OPL，在OPL顶部的可显影抗反射涂层（DARC）层和DARC层顶部的光致抗蚀剂层的块掩模叠层用于掩蔽一种导电类型的FinFET，同时在源极/漏极离子注入期间露出另一导电类型的FinFET。 OPL被配置为具有足以填充半导体翅片之间的空间并覆盖半导体翅片的最小厚度。 DARC层被配置为平面化半导体鳍片的形貌，以便为随后的光刻和蚀刻工艺提供平坦的顶表面。