公开(公告)号：US20200381476A1

公开(公告)日：2020-12-03

申请号：US16425360

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: H01L27/22 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  G11C11/16 ,  H01L43/10 ,  H01F41/32 ,  H01F10/32 ,  H01L43/02 ,  G11C13/00

Abstract: Structures for a bitcell of a non-volatile memory and methods of fabricating and using such structures. Non-volatile memory elements are arranged in a Wheatstone bridge arrangement having a first terminal and a second terminal. A first field-effect transistor is coupled with the first terminal of the Wheatstone bridge arrangement, and a second field-effect transistor is coupled with the second terminal of the Wheatstone bridge arrangement.

公开(公告)号：US10672465B1

公开(公告)日：2020-06-02

申请号：US16388607

申请日：2019-04-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Amogh Agrawal ,  Ajey Poovannummoottil Jacob

IPC: G11C11/00 ,  G11C11/54 ,  G11C14/00 ,  G06N3/00 ,  G11C11/417 ,  G11C11/16 ,  G11C11/412

Abstract: One illustrative device includes, among other things, a first resistive storage element; a second resistive storage element; and logic to couple the first resistive storage element and the second resistive storage element in a series arrangement in a first configuration and to couple the first resistive storage element and the second resistive storage element in a parallel arrangement in a second configuration.

公开(公告)号：US10665281B1

公开(公告)日：2020-05-26

申请号：US16286942

申请日：2019-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal ,  Bipul C. Paul

IPC: G11C11/16 ,  H01L27/22

Abstract: A device is disclosed including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.

公开(公告)号：US20200243126A1

公开(公告)日：2020-07-30

申请号：US16261617

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/16 ,  G11C13/00

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

公开(公告)号：US10726896B1

公开(公告)日：2020-07-28

申请号：US16261617

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.