公开(公告)号：US20160079086A1

公开(公告)日：2016-03-17

申请号：US14484770

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Hans-Juergen Thees ,  Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L21/3213 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32132 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Abstract translation: 本公开提供了一种形成半导体器件的方法，包括半导体器件的栅极结构的成形，使得避免了形成硅化物之后的间隔物去除并且抑制了硅化物突出。 在本公开的一些方面，提供一种形成半导体器件的方法，其中栅极结构设置在半导体衬底的有源区上方，栅极结构包括栅电极材料和侧壁间隔物。 通过对栅极结构施加成形工艺来形成栅电极材料和侧壁间隔物中的至少一个，并且在成形栅极结构上形成硅化物部分。

公开(公告)号：US10115621B2

公开(公告)日：2018-10-30

申请号：US15153936

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Moll ,  Martin Schmidt ,  Carsten Hartig ,  Matthias Ruhm ,  Stefan Thierbach ,  Stefan Rongen ,  Daniel Fischer ,  Andreas Schuring ,  Guido Überreiter

IPC: H01L21/68 ,  H01L23/544 ,  G03F7/20 ,  G03F9/00 ,  H01L21/66

Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.

公开(公告)号：US09761689B2

公开(公告)日：2017-09-12

申请号：US14484770

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Hans-Juergen Thees ,  Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32132 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

公开(公告)号：US09196684B2

公开(公告)日：2015-11-24

申请号：US14254710

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Frohberg ,  Peter Moll ,  Dominik Olligs ,  Heike Scholz

IPC: H01L21/8238 ,  H01L29/10

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7843

Abstract: A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET.

Abstract translation: 公开了一种减少FEoL地形对双应力衬垫沉积物的影响的方法和所得到的装置。 实施例包括在pFET和nFET之间和之上形成第一氮化物层; 使第一氮化物层变薄; 在所述第一氮化物层上形成第二氮化物层; 以及从pFET上方去除第一和第二氮化物层。

公开(公告)号：US09159661B2

公开(公告)日：2015-10-13

申请号：US14083797

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L23/58 ,  H01L23/532 ,  H01L29/772 ,  H01L29/92 ,  H01L21/20 ,  H01L23/498 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point.

Abstract translation: 提供具有紧密电接触的集成电路和用于制造这种集成电路的方法。 该方法包括在层间电介质中形成第一和第二接触，并且在第一和第二接触之间形成凹陷。 形成覆盖在层间电介质上的蚀刻掩模，并且从凹陷中点上方去除蚀刻掩模。 在凹陷中点处的层间电介质中形成中心接触。

公开(公告)号：US20150137385A1

公开(公告)日：2015-05-21

申请号：US14083797

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/321

CPC classification number: H01L23/49827 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point.

Abstract translation: 提供具有紧密电接触的集成电路和用于制造这种集成电路的方法。 该方法包括在层间电介质中形成第一和第二接触，并且在第一和第二接触之间形成凹陷。 形成覆盖在层间电介质上的蚀刻掩模，并且从凹陷中点上方去除蚀刻掩模。 在凹陷中点处的层间电介质中形成中心接触。