公开(公告)号：US20190214387A1

公开(公告)日：2019-07-11

申请号：US15868058

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  George Mulfinger ,  Timothy J. McArdle ,  Thomas Merbeth ,  Ömür Aydin ,  Ruilong Xie

IPC: H01L27/092 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/41775 ,  H01L29/66515

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.

公开(公告)号：US10388654B2

公开(公告)日：2019-08-20

申请号：US15868058

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  George Mulfinger ,  Timothy J. McArdle ,  Thomas Merbeth ,  Ömür Aydin ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.

公开(公告)号：US10217660B2

公开(公告)日：2019-02-26

申请号：US15652585

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  George Mulfinger

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/308 ,  H01L29/06

Abstract: When patterning active regions for sophisticated semiconductor devices, the cutting through active semiconductor regions previously patterned along a first lateral direction so as to obtain elongated semiconductor lines may be performed in a late manufacturing stage. That is, the cutting may be performed after patterning at least a portion of the gate electrode structures, thereby achieving a self-aligned patterning regime and also contributing to a reduction of strain loss.

公开(公告)号：US20190027400A1

公开(公告)日：2019-01-24

申请号：US15652585

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  George Mulfinger

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/308 ,  H01L29/06

Abstract: When patterning active regions for sophisticated semiconductor devices, the cutting through active semiconductor regions previously patterned along a first lateral direction so as to obtain elongated semiconductor lines may be performed in a late manufacturing stage. That is, the cutting may be performed after patterning at least a portion of the gate electrode structures, thereby achieving a self-aligned patterning regime and also contributing to a reduction of strain loss.

公开(公告)号：US10056381B2

公开(公告)日：2018-08-21

申请号：US15259268

申请日：2016-09-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  Amy Child ,  George Mulfinger

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/225 ,  H01L21/308 ,  H01L21/324 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/2256 ,  H01L21/308 ,  H01L21/324 ,  H01L21/823821 ,  H01L29/1083 ,  H01L29/167

Abstract: Device structures for a FinFET and fabrication methods for making a device structure for a FinFET. A first layer containing a first dopant is formed on a first region of a substrate. A second layer containing a second dopant is formed on a second region of the substrate. A first plurality of fins are formed and are each located in a respective trench extending from the substrate through the first layer. A second plurality of fins are formed and are each located in a respective trench extending from the substrate through the second layer. The first dopant is transferred from the first layer to a first section in each of the first plurality of fins and the second dopant is transferred from the second layer to a first section in each of the second plurality of fins.

公开(公告)号：US20180069005A1

公开(公告)日：2018-03-08

申请号：US15259268

申请日：2016-09-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  Amy Child ,  George Mulfinger

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/225 ,  H01L21/308 ,  H01L21/324 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/2256 ,  H01L21/308 ,  H01L21/324 ,  H01L21/823821 ,  H01L29/1083 ,  H01L29/167

Abstract: Device structures for a FinFET and fabrication methods for making a device structure for a FinFET. A first layer containing a first dopant is formed on a first region of a substrate. A second layer containing a second dopant is formed on a second region of the substrate. A first plurality of fins are formed and are each located in a respective trench extending from the substrate through the first layer. A second plurality of fins are formed and are each located in a respective trench extending from the substrate through the second layer. The first dopant is transferred from the first layer to a first section in each of the first plurality of fins and the second dopant is transferred from the second layer to a first section in each of the second plurality of fins.