公开(公告)号：US08839168B2

公开(公告)日：2014-09-16

申请号：US13746508

申请日：2013-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jongwook Kye ,  Harry J Levinson ,  Jason E Stephens ,  Lei Yuan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.

Abstract translation: 公开了一种用于确定与自对准双重图案（SADP）技术一起使用的通孔外壳规则的设计方法。 块掩模的形状作为选择通孔封套规则的标准。 集成电路设计中不同的块掩模形状可以利用不同的规则，并为通孔外壳提供不同的边缘。 紧密的通孔外壳设计规则可能会减少超出通孔的线的余量，而松动的通孔外壳设计规则可增加超出通孔的线的裕度，从而有利于此。

公开(公告)号：US09536778B2

公开(公告)日：2017-01-03

申请号：US14679060

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J Levinson

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257

Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Abstract translation: 公开了用于在导线之间产生金属路径的自对准双重图案化工艺。 实施例包括在电介质层上形成硬掩模; 在硬掩模上形成包括多个平行线形元件的图案化模板，其中所述硬掩模在相邻的平行线性元件之间露出; 形成覆盖所述相邻的平行线性元件的一部分和其间的空间的块掩模; 通过所述块掩模蚀刻所述硬掩模的暴露部分和限定多条平行线的所述图案化模板; 去除所述块掩模和所述图案化模板; 在所述硬掩模上形成切割掩模以限定垂直于并连接两个相邻平行线的开口; 通过所述切割掩模蚀刻所述硬掩模并除去切割的掩模; 通过所述硬掩模蚀刻介电层中的凹槽; 去除硬面膜; 并用导电材料填充所述凹部。