公开(公告)号：US09323882B2

公开(公告)日：2016-04-26

申请号：US14228611

申请日：2014-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Guido Ueberreiter ,  Lloyd C. Litt ,  Paul Ackmann

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract translation: 提供了一种用于电路结构的度量图案布局，包括多个象限的计量图案布局，其中可以将象限第一晶片测量图案，第二晶片测量图案，标线片配准图案和掩模版测量图案布置成 有助于光栅测量数据与晶圆计量数据的相关性。 标线片配准图案还可以包括被设计成保护掩模版测量图案内的其它结构元件的一个或多个最外面的结构元件在光学邻近校正过程中被修改。 提供了一种光学邻近校正处理方法，其中可以获得分划板测量图案并将其分类以添加或修改光学邻近校正处理的规则集。

公开(公告)号：US09864831B2

公开(公告)日：2018-01-09

申请号：US15071890

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Guido Ueberreiter ,  Lloyd C. Litt ,  Paul Ackmann

IPC: G06F17/00 ,  G06F17/50 ,  G03F1/36 ,  G03F7/20 ,  G03F1/68

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

公开(公告)号：US20190278166A1

公开(公告)日：2019-09-12

申请号：US15915280

申请日：2018-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Guoxiang Ning ,  Lloyd C. Litt

IPC: G03F1/58 ,  H01L21/027 ,  G03F1/64 ,  G03F7/20 ,  G03F1/22

Abstract: Disclosed is a reticle with multiple different sets of redundant mask patterns. Each set allows for patterning of a layer at a specific level of an integrated circuit (IC) chip design on a target region of a wafer using a vote-taking technique to avoid defects. The different sets further allow the same reticle to be used to pattern layers at different levels in the same IC chip design or to pattern layers at the same level or at different levels in different IC chip designs. Each mask pattern is individually framed with alignment marks to facilitate alignment minimize overlay errors. Optionally, redundant mask patterns in the same set are distributed across the reticle (as opposed to being located within the same general area) in order to minimize reticle overheating during patterning using the vote-taking technique. Also disclosed are a photolithography system and a photolithography method that employ such a reticle.