公开(公告)号：US10896874B2

公开(公告)日：2021-01-19

申请号：US16363585

申请日：2019-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Ruilong Xie ,  Lei Sun

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

公开(公告)号：US10727120B2

公开(公告)日：2020-07-28

申请号：US16111193

申请日：2018-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean X Lin ,  Ruilong Xie ,  Guoxiang Ning ,  Lei Sun

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

公开(公告)号：US10685874B1

公开(公告)日：2020-06-16

申请号：US16220565

申请日：2018-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Lei Sun ,  Lars Liebmann ,  Daniel Chanemougame ,  Guillaume Bouche

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.

公开(公告)号：US10468149B2

公开(公告)日：2019-11-05

申请号：US15424200

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yulu Chen ,  Francis Goodwin ,  Jed Rankin ,  Lei Sun ,  Obert Reeves Wood, II

IPC: G02B5/08 ,  G02B5/20 ,  F21V9/04 ,  F21V9/06 ,  G21K1/06 ,  G03F1/24 ,  G02B27/00 ,  G03F7/20 ,  G01M11/00

Abstract: Extreme ultraviolet mirrors and masks used in lithography and methods for manufacturing an extreme ultraviolet mirror or mask. Initial data is obtained that includes materials and optical properties for a first intermixed layer, a second intermixed layer, a first pure layer, and a second pure layer in each of a plurality of periods of a multi-layer stack for an optical element. For multiple thicknesses for the first pure layer and multiple thicknesses for the second pure layer, a reflectivity of the multi-layer stack is determined based on the initial data, a thickness received for the first intermixed layer, and a thickness received for the second intermixed layer. One of the thicknesses for the first pure layer and one of the thicknesses for the second pure layer are selected that maximize the reflectivity of the multi-layer stack.

公开(公告)号：US20190148373A1

公开(公告)日：2019-05-16

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/0276 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US10211147B2

公开(公告)日：2019-02-19

申请号：US15643032

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Lei Sun ,  Yi Qi ,  Roderick Augur

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.

公开(公告)号：US20190013269A1

公开(公告)日：2019-01-10

申请号：US15643032

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Lei Sun ,  Yi Qi ,  Roderick Augur

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.

公开(公告)号：US09484258B1

公开(公告)日：2016-11-01

申请号：US15071247

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han Kim ,  Wenhui Wang ,  Lei Sun ,  Erik Verduijn ,  Yulu Chen

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528

Abstract: A method for producing self-aligned vias (SAV) is provided. Embodiments include forming a ILOS layer over a dielectric layer; forming pairs of spacers over the ILOS layer, each pair of spacers having a first filler formed between adjacent spacers, and a second filler formed between each pair of spacers; forming and patterning a first OPL to expose one second filler, spacers on opposite sides of the one second filler, and a portion of the first filler adjacent each of the exposed spacers; removing the one second filler to form a SAV, and SAV etching into the ILOS layer; forming a second OPL over the first OPL and in the SAV to form a SAV plug; removing OPL layers and etching into the ILOS layer down to the dielectric layer; forming a third OPL layer in spaces between the TEOS layer; and removing the SAV plug.

Abstract translation: 提供了一种生产自对准通孔（SAV）的方法。 实施例包括在电介质层上形成ILOS层; 在ILOS层上形成隔离物对，每对隔离物具有形成在相邻间隔物之间​​的第一填料和在每对隔离物之间形成的第二填料; 形成和图案化第一OPL以暴露一个第二填料，一个第二填料的相对侧上的间隔物和与每个暴露间隔物相邻的第一填料的一部分; 去除一个第二填料以形成SAV，并且SAV蚀刻到ILOS层中; 在第一OPL和SAV上形成第二OPL以形成SAV插头; 去除OPL层并蚀刻到ILOS层中直到电介质层; 在TEOS层之间的空间中形成第三OPL层; 并卸下SAV插头。

公开(公告)号：US09478462B1

公开(公告)日：2016-10-25

申请号：US15071255

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Lei Sun ,  Erik Verduijn ,  Yulu Chen

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/76808 ,  H01L21/76897 ,  H01L23/5226

Abstract: Methods of forming a SAV using a selective SAQP or SADP process are provided. Embodiments include providing on a TiN layer and dielectric layers alternating mandrels and non-mandrel fillers, spacers therebetween, and a metal cut plug through a mandrel or a non-mandrel filler; removing a non-mandrel filler through a SAV patterning stack having an opening over the non-mandrel filler and adjacent spacers, forming a trench; removing a mandrel through a second SAV patterning stack having an opening over the mandrel and adjacent spacers, forming a second trench; etching the trenches through the TiN and dielectric layers; forming plugs in the trenches; removing the mandrels and non-mandrel fillers, forming third trenches; etching the third trenches through the TiN layer; removing the metal cut plug and spacers and etching the third trenches into the dielectric layer; removing the plugs; and filling the trenches with metal.

Abstract translation: 提供了使用选择性SAQP或SADP方法形成SAV的方法。 实施例包括在TiN层和介电层上提供交替的心轴和非心轴填料，间隔件和通过心轴或非心轴填料的金属切割塞; 通过具有在非芯棒填料和相邻间隔物上的开口的SAV图案化叠层去除非芯棒填料，形成沟槽; 通过具有在所述心轴和相邻间隔物上的开口的第二SAV图案化叠层移除心轴，形成第二沟槽; 通过TiN和电介质层蚀刻沟槽; 在沟槽中形成插塞; 去除心轴和非心轴填料，形成第三沟槽; 蚀刻通过TiN层的第三沟槽; 去除金属切割塞子和间隔件并将第三沟槽蚀刻到介电层中; 取下插头; 并用金属填充沟槽。

公开(公告)号：US20150036978A1

公开(公告)日：2015-02-05

申请号：US13958190

申请日：2013-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Obert Reeves Wood, II

IPC: G02B5/20 ,  G02B1/12

CPC classification number: G02B5/20 ,  G02B1/12 ,  G02B5/203

Abstract: A novel blazed grating spectral filter disclosed herein includes a multilayer stack of materials that is formed on a wedge-shaped substrate wherein the upper surface of the substrate is oriented at an angle relative the bottom surface of the substrate and wherein the angle corresponds to the blaze angle of the blazed grating filter. Various methods of forming such a filter are also disclosed such as, for example, performing a planarization process in a CMP tool to define the wedge-shaped substrate, thereafter forming the multilayer stack of materials above the upper planarized surface of the substrate and etching recesses into the multilayer stack.

Abstract translation: 本文公开的新型闪耀光栅光谱滤波器包括形成在楔形衬底上的多层材料堆叠，其中衬底的上表面相对于衬底的底表面以一定角度取向，并且其中该角度对应于火焰 闪光光栅滤光片的角度。 还公开了形成这种滤光器的各种方法，例如，在CMP工具中执行平坦化处理以限定楔形基板，之后在基板的上平面化表面上方形成多层堆叠的材料，并且蚀刻凹槽 进入多层堆叠。