公开(公告)号：US20150340229A1

公开(公告)日：2015-11-26

申请号：US14282094

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Neeraj TRIPATHI ,  Christopher Michael PRINDLE

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/02494 ,  H01L21/02658 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/78

Abstract: Field-effect transistors (FETs) and methods of fabricating field-effect transistors are provided, with one or both of a source cavity or a drain cavity having different channel junction characteristics. The methods include, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of the transistor, the recessing defining a bottom channel interface surface and a sidewall channel interface surface within the cavity; providing a protective liner over the sidewall channel interface surface, with the bottom channel interface surface being exposed within the cavity; processing the bottom channel interface surface to facilitate forming a first channel junction of the transistor; and removing the protective liner from over the sidewall channel interface surface, and subsequently processing the sidewall channel interface surface to form a second channel junction of the transistor, where the first and second channel junctions have different channel junction characteristics.

Abstract translation: 提供场效应晶体管（FET）和制造场效应晶体管的方法，其中源腔或漏腔中的一个或两个具有不同的沟道结特征。 所述方法包括例如使半导体材料凹陷以形成与晶体管的沟道区相邻的空腔，所述凹陷限定所述空腔内的底部沟道界面表面和侧壁通道界面表面; 在所述侧壁通道界面表面上提供保护衬垫，所述底部通道界面表面暴露在所述空腔内; 处理底部通道界面以便于形成晶体管的第一通道结; 以及从所述侧壁通道界面表面上移除所述保护性衬垫，以及随后处理所述侧壁通道界面以形成所述晶体管的第二通道结，其中所述第一和第二通道结具有不同的通道结特性。

公开(公告)号：US20170062429A1

公开(公告)日：2017-03-02

申请号：US15172201

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Neeraj TRIPATHI

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66803 ,  H01L29/66818

Abstract: A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.

Abstract translation: 提供了形成翅片衬垫的方法和所得到的装置。 实施例包括在衬底的负沟道场效应晶体管（nFET）和正沟道场效应晶体管（pFET）区域上形成硅（Si）鳍，每个Si散热片具有氮化硅（SiN）帽; 在Si翅片和SiN帽上形成SiN衬垫; 在所述pFET区域上形成块掩模; 去除nFET区域中的SiN衬垫; 去除pFET区域中的块掩模; 在Si散热片上形成扩散阻挡衬垫; 在Si散热片之上和之间形成介电层; 将电介质层平坦化到nFET区域中的SiN帽; 并使介电层凹陷以暴露Si散热片的上部。

公开(公告)号：US20170077234A1

公开(公告)日：2017-03-16

申请号：US14853303

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Neeraj TRIPATHI ,  Srinivasa R. BANNA

IPC: H01L29/161 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/02532 ,  H01L21/0245 ,  H01L21/02664 ,  H01L21/76208

Abstract: Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films for semiconductor devices are provided. One method includes, for instance: obtaining a wafer including a substrate; epitaxially growing at least one first silicon germanium (SiGe) layer over the wafer; and epitaxially growing at least one second SiGe layer over the at least one first SiGe layer. One device includes, for instance: a wafer including a substrate; at least one first layer of semiconductor material disposed over the wafer; at least one second layer of semiconductor material disposed over the at least one first layer of semiconductor material; and at least one first and second openings, each opening extending through the at least one second layer of semiconductor material, the at least one first layer of semiconductor material, and a portion of the substrate.

Abstract translation: 提供了用于半导体器件的外延生长的晶格失配膜的弹性松弛的装置和方法。 一种方法包括例如：获得包括衬底的晶片; 在晶片上外延生长至少一个第一硅锗（SiGe）层; 以及在所述至少一个第一SiGe层上外延生长至少一个第二SiGe层。 一个装置包括例如：包括衬底的晶片; 设置在所述晶片上方的至少一个第一半导体材料层; 设置在所述至少一个第一半导体材料层上的至少一个第二半导体材料层; 以及至少一个第一和第二开口，每个开口延伸穿过所述至少一个第二半导体材料层，所述至少一个第一半导体材料层和所述衬底的一部分。