公开(公告)号：US20170336467A1

公开(公告)日：2017-11-23

申请号：US15156814

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo Pablo. Mikalo ,  Stefan Richter ,  Christian Schippel ,  Michael Zier

IPC: G01R31/26 ,  H01L27/12 ,  H01L23/528 ,  H01L23/525 ,  H01L21/84 ,  H01L27/092 ,  H01L29/78

CPC classification number: G01R31/2621 ,  G01R31/2884 ,  H01L21/84 ,  H01L23/5256 ,  H01L23/528 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78

Abstract: A test structure for a semiconductor device, comprising a device under test including a transistor, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, a first fuse and a second fuse provided in series, wherein one terminal of the first fuse is connected to the gate electrode, one terminal of the second fuse is connected to the bulk electrode, the other terminal of the first fuse and the other terminal of the second fuse being connected to each other, a first input/output pad connected to the first terminal of the first fuse and to the gate electrode of the transistor, a second input/output pad connected to the first terminal of the second fuse and to the bulk electrode of the transistor, a third input/output pad connected to the second terminal of the first fuse and the second terminal of the second fuse.

公开(公告)号：US20160266200A1

公开(公告)日：2016-09-15

申请号：US14645541

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo Pablo. Mikalo

IPC: G01R31/30 ,  G01R31/28

CPC classification number: G01R31/3008 ,  G01R31/025 ,  G01R31/2851

Abstract: A test configuration for testing a leakage current of a device under test (DUT) of an integrated circuit is provided including a logarithmic transducer electrically connected to the DUT and a voltmeter electrically connected to the logarithmic transducer.

Abstract translation: 提供了用于测试集成电路的被测器件（DUT）的漏电流的测试配置，包括电连接到DUT的对数换能器和电连接到对数换能器的电压计。

公开(公告)号：US20170287901A1

公开(公告)日：2017-10-05

申请号：US15089914

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Dersch ,  Ricardo Pablo. Mikalo

IPC: H01L27/06 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0629 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/66166 ,  H01L29/7838 ,  H01L29/8605

Abstract: A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping.

公开(公告)号：US20150349120A1

公开(公告)日：2015-12-03

申请号：US14719424

申请日：2015-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo Pablo. Mikalo ,  Joachim Deppe

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L27/12

CPC classification number: G06F19/321 ,  G06F19/00 ,  G16H50/70 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/41766 ,  H01L29/7835

Abstract: A semiconductor device structure includes a semiconductor substrate with an active region provided therein, a gate structure, a dummy gate structure and two contact regions provided in the active region for forming source and drain regions. The gate structure and the dummy gate structure are formed on the semiconductor substrate so as to partially overlie the active region, and one of the contact regions is located at one side of the dummy gate structure. The semiconductor device structure includes a contact structure contacting one of the contact regions and the dummy gate for connecting this contact region and the dummy gate to one of a Vdd rail and a Vss rail. The active region has an extension portion protruding laterally away from the active region relative to the other contact region, where the contact structure is located over the extension portion.

Abstract translation: 半导体器件结构包括其中设置有有源区的半导体衬底，栅极结构，虚拟栅极结构和设置在用于形成源极和漏极区域的有源区中的两个接触区域。 栅极结构和虚拟栅极结构形成在半导体衬底上以部分覆盖有源区，并且一个接触区位于虚拟栅极结构的一侧。 半导体器件结构包括接触结构中的一个接触区域和伪栅极，用于将该接触区域和虚拟栅极连接到Vdd轨道和Vss轨道之一。 有源区域具有相对于另一接触区域横向远离有源区域突出的延伸部分，其中接触结构位于延伸部分上方。

公开(公告)号：US09786657B1

公开(公告)日：2017-10-10

申请号：US15089914

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Dersch ,  Ricardo Pablo. Mikalo

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0629 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/66166 ,  H01L29/7838 ,  H01L29/8605

Abstract: A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping.

公开(公告)号：US09613181B2

公开(公告)日：2017-04-04

申请号：US14719424

申请日：2015-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo Pablo. Mikalo ,  Joachim Deppe

IPC: H01L27/088 ,  G06F19/00 ,  H01L29/78 ,  H01L27/12 ,  H01L29/417

CPC classification number: G06F19/321 ,  G06F19/00 ,  G16H50/70 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/41766 ,  H01L29/7835

Abstract: A semiconductor device structure includes a semiconductor substrate with an active region provided therein, a gate structure, a dummy gate structure and two contact regions provided in the active region for forming source and drain regions. The gate structure and the dummy gate structure are formed on the semiconductor substrate so as to partially overlie the active region, and one of the contact regions is located at one side of the dummy gate structure. The semiconductor device structure includes a contact structure contacting one of the contact regions and the dummy gate for connecting this contact region and the dummy gate to one of a Vdd rail and a Vss rail. The active region has an extension portion protruding laterally away from the active region relative to the other contact region, where the contact structure is located over the extension portion.

公开(公告)号：US20170067955A1

公开(公告)日：2017-03-09

申请号：US14848804

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Uwe Dersch ,  Ricardo Pablo. Mikalo

IPC: G01R31/26 ,  G01R31/02 ,  H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/08

CPC classification number: G01R31/2621 ,  G01R31/2884 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/42384

Abstract: A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.

Abstract translation: 提供半导体测试结构用于检测凸起的源极/漏极区域 - 包括半导体衬底的栅极电极短路，形成在半导体衬底上的FET，形成在半导体衬底上的FET的升高的源极/漏极区域，包括多个 所述FET的栅电极彼此平行地布置，以及电连接到所述栅电极结构的第一电端子，并且其中在所述栅极电极结构的所述多个栅电极之间没有与所述凸起的源极/漏极区的电接触。