公开(公告)号：US20150311272A1

公开(公告)日：2015-10-29

申请号：US14261021

申请日：2014-04-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alexandru Romanescu ,  Gerd Zschätzsch ,  Christian Schippel

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/28

CPC classification number: H01L27/0629 ,  H01L28/24 ,  H01L29/665 ,  H01L29/78

Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.

Abstract translation: 提供了具有由栅极金属形成的电阻结构的集成电路及其制造方法。 在一个实施例中，制造集成电路的方法包括：提供具有电阻区域和晶体管区域的半导体衬底。 该方法在电阻器区域和半导体衬底的晶体管区域上沉积栅极金属，并且栅极金属在电阻器区域中形成栅极金属层。 该方法包括蚀刻栅极金属以从电阻器区域中的栅极金属层形成电阻器结构。 此外，该方法包括在电阻器区域中形成与电阻器结构的接触。

公开(公告)号：US20180204944A1

公开(公告)日：2018-07-19

申请号：US15405495

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Andrei Sidelnicov ,  Gerd Zschaetzsch

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7824 ,  H01L21/28052 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/78648

Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.

公开(公告)号：US10056481B2

公开(公告)日：2018-08-21

申请号：US15405495

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Andrei Sidelnicov ,  Gerd Zschaetzsch

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7824 ,  H01L21/28052 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/78624 ,  H01L29/78648

Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.

公开(公告)号：US10038091B2

公开(公告)日：2018-07-31

申请号：US15198038

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/167 ,  H01L29/06 ,  H01L29/45 ,  H01L21/265 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: The present disclosure provides a semiconductor device including a substrate, a first well and a second well formed in the substrate, the first well being doped with dopants of a first conductivity type and the second well being doped with dopants of a second conductivity type, a third well within the first well, a gate structure partially formed over the first and second wells, and a first epi region on the third well and a drain region electrically coupled to the second well, the first epi region being doped with dopants of the second conductivity type.

公开(公告)号：US20170125610A1

公开(公告)日：2017-05-04

申请号：US14928595

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/49 ,  H01L27/06 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.

公开(公告)号：US10886419B2

公开(公告)日：2021-01-05

申请号：US15913344

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49 ,  H01L29/78 ,  H01L29/93 ,  H01L29/66

Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.

公开(公告)号：US20180254343A1

公开(公告)日：2018-09-06

申请号：US15971419

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L29/45 ,  H01L29/167 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7824 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a first conductivity type and the second well is doped with dopants of a second conductivity type. A third well is formed within the first well, and a gate structure is formed above the substrate, the gate structure partially overlying at least the first and second wells. A first epi region is formed on the third well, wherein the first epi region is doped with second dopants of the second conductivity type, and a drain region is formed that is electrically coupled to the second well.

公开(公告)号：US20170336467A1

公开(公告)日：2017-11-23

申请号：US15156814

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo Pablo. Mikalo ,  Stefan Richter ,  Christian Schippel ,  Michael Zier

IPC: G01R31/26 ,  H01L27/12 ,  H01L23/528 ,  H01L23/525 ,  H01L21/84 ,  H01L27/092 ,  H01L29/78

CPC classification number: G01R31/2621 ,  G01R31/2884 ,  H01L21/84 ,  H01L23/5256 ,  H01L23/528 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78

Abstract: A test structure for a semiconductor device, comprising a device under test including a transistor, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, a first fuse and a second fuse provided in series, wherein one terminal of the first fuse is connected to the gate electrode, one terminal of the second fuse is connected to the bulk electrode, the other terminal of the first fuse and the other terminal of the second fuse being connected to each other, a first input/output pad connected to the first terminal of the first fuse and to the gate electrode of the transistor, a second input/output pad connected to the first terminal of the second fuse and to the bulk electrode of the transistor, a third input/output pad connected to the second terminal of the first fuse and the second terminal of the second fuse.

公开(公告)号：US09530770B2

公开(公告)日：2016-12-27

申请号：US14261021

申请日：2014-04-24

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Alexandru Romanescu ,  Gerd Zschätzsch ,  Christian Schippel

IPC: H01L21/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L28/24 ,  H01L29/665 ,  H01L29/78

Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.

Abstract translation: 提供了具有由栅极金属形成的电阻结构的集成电路及其制造方法。 在一个实施例中，制造集成电路的方法包括：提供具有电阻区域和晶体管区域的半导体衬底。 该方法在电阻器区域和半导体衬底的晶体管区域上沉积栅极金属，并且栅极金属在电阻器区域中形成栅极金属层。 该方法包括蚀刻栅极金属以从电阻器区域中的栅极金属层形成电阻器结构。 此外，该方法包括在电阻器区域中形成与电阻器结构的接触。

公开(公告)号：US20150179753A1

公开(公告)日：2015-06-25

申请号：US14136815

申请日：2013-12-20

Applicant: Globalfoundries Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Maciej Wiatr ,  Christian Schippel

IPC: H01L29/49 ,  H01L21/285 ,  H01L23/62

CPC classification number: H01L29/4975 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract translation: 电子熔断器用于集成电路，以便在制造后允许电路的实时动态重新编程。 因此提出了一种电熔丝，其中适于在电流通过时被吹塑的金属元件不是由硅化物层组成的，而是一个金属层，其上形成半导体层。 然后在半导体层上形成电介质层，以防止在金属层上形成金属硅化物。 电子熔断器的制造过程可以很容易地集成在HKMG制造流程中。 特别地，完全硅化金属栅极可以与电熔丝一起制造，而不会危及电子熔丝的正确功能。